PIn Assignment & Power-Ground Routing in Physical Design

 

Design Flow and Pin Assignment :

When planning the layout of large blocks, where you place the connection points (terminals) is very important. These connection points, called I/O pins, are usually placed on the edges of the blocks to keep the wiring short. The best spots for these pins depend on how the blocks are arranged. During pin assignment, each signal (net) is assigned a specific pin location to improve the overall design. The main goals are to make sure the wiring is easy to route and to reduce unwanted electrical effects both inside and outside the block. The objective of external pin assignment is to link each incoming or outgoing signal to a unique I/O pin. After assigning each necessary net to its designated pin, the connections must be optimized to minimize wire length and reduce electrical parasitics, such as coupling or signal integrity loss.

More on Pin Assignment :

Pin assignment is used to connect cell pins that are functionally or electrically equivalent, such as during standard cell placement. Two pins are considered functionally equivalent if swapping them does not alter the design's logic, and they are electrically equivalent or equi-potential if they are connected. The primary goal of internal pin assignment for cells is to minimize congestion and reduce interconnect length between cells.  The pin assignment techniques described below are applicable to both chip planning and placement stages.

Pin Assignment using Concentric Circles :

The algorithm connect a block to all its associated pins in other blocks with minimum of cross-connections. It operates under the assumption that all outer pins have fixed positions. Inner pins are positioned based on the locations of their electrically equivalent outer pins. The algorithm employs two concentric circles: the inner circle for the pins of the block being considered and the outer circle for pins in other blocks. The primary goal is to assign valid pin locations on both circles w/o no net overlap.

1. Determine the Circles : 

The two circles are drawn such a way that all pins that belong to the block are outside the inner circle and all external pins are outside the outer circle.

2. Determine the Points :

For each point, draw a line from that point to the center of the circles. Then, move each outer point to where the line meets the outer circle, and move each inner point to where the line meets the inner circle.

3. Determine Initial Mapping : 

The initial setup pairs each outer pin with a matching inner pin. Start by choosing any pin and assign it to an inner pin. Then, assign the rest of the pins either in a clockwise or anti-clockwise direction.

4. Optimizing the Mapping :

Repeat the process of pairing outer and inner points in different ways. Start with the same outer point, but try pairing it with different inner points, and then pair the rest of the points accordingly. Continue until all possible pairings have been tried. The best pairing is the one that has the shortest total distance between the points. In this problem, an example pairing is shown on the left, the best pairing is in the center, and the final pin assignments are on the right.

Topological Pin Assignment :

This algorithm is an improvement to concentric-circle pin assignment algorithm. It takes into account external block positions and multi -pin nets. This allowed pin assignment even when external pins are behind other blocks. This algorithm is an improvement to concentric-circle pin assignment algorithm. It takes into account external block positions and multi -pin nets. This allowed pin assignment even when external pins are behind other blocks.

This method allows multiple block to be considered simultaneously. There are two blocs a & b. On block a, consider the midpoint lines lm~a and lm~b. The point d1 is formed because it is the farther point on lm~a. The point d2 is formed because it is closer point on lm~b.  The point d3 is formed because it is the farther oint on lm~b. Using d1-d3, the pins are “unwrapped” accordingly when projected onto m’s outer circle.

Design Flow : Power & Ground Routing :

Chip planning involves designing the power-ground distribution network and positioning supply I/O pads or bumps. Up to 20-40% of all metal resources on the chip are used to supply power (VDD) and ground (GND) nets.

The power planning process includes iterative steps such as:

1. Early simulation of major power dissipation components.

2. Initial estimation of overall chip power.

3. Analysis of total chip power and peak power density.

4. Examination of total chip power fluctuations.

5. Analysis of inherent and additional fluctuations caused by        clock gating.

6. Early analysis of power distribution, including average, maximum, and multi-cycle fluctuations.

Design of a Power-Ground Distribution :

Every cell needs both VDD and GND connections. They connect each cell in the design to a power source. VDD and GND supply lines are large, cover the entire chip, and are routed before any signal lines. Core supply lines differ from I/O supply lines, which usually have a higher voltage. Single core power line and core ground line are often enough, For some ICs, like mixed-signal or low-power designs, may have multiple power and ground lines. Routing power/ground lines is different from routing signal lines. Power/ground lines require their own metal layers to avoid taking up space needed for signal routing. Thicker metal layers, typically the top two in the manufacturing process, are preferred for power and ground lines due to their lower resistance. When the power-ground network spans multiple layers, sufficient vias must be used to carry current and prevent reliability issues like electro-migration. Supply lines carry high current, so they are often much wider than signal lines. The width of each wire segment can be adjusted based on the expected current. Wider segments have lower resistance, which reduces voltage drop. 

 There are two main approaches to designing power-ground distribution:

1. The planar approach : used in analog or custom blocks.

2. The mesh approach : more common in digital ICs.

Planar Routing:

Power supply nets can be routed using planar routing when 

(1) only two supply nets are present in the design,

(2) a cell needs a connection to both supply nets.

A Hamiltonian path is created that connects all the cells. The path divides the layout into two regions: one for each supply net. Each supply net is routed either the left/right side of the path for each cell. So both supply nets can be laid out without conflicts in across the design.

Routing the power and grounds nets and grounds nets in this planar fashion can be accomplished with the following three steps:

1. Planarize the topology of nets:

Since both power and ground nets must be routed on the same layer, the design should be divided using a Hamiltonian path. Start routing the power and ground nets from the left and right sides, respectively. Ensure both nets expand in a tree-like structure,  avoiding overlap and maintaining separation by the Hamiltonian path. The precise routing will depend on the pin locations. Connect the cells wherever a pin is encountered during the routing process.

2. Layer Assignment :

Net segments are allocated to specific routing layers considering factors such as routability, the resistance and capacitance characteristics of each available layer, and design rule constraints.

3. Determining the widths of the net segment:

The width of each segment is based on the maximum current it needs to carry. This width is determined by summing up the currents from all the connected cells, according to Kirchhoff's Current Law (KCL). For large currents, designers often increase the width by stacking multiple layers vertically, connected by vias. Deciding the right width is usually an iterative process because currents are influenced by timing and noise, which are, in turn, affected by voltage drops, creating a cyclic dependency. This loop is typically resolved through multiple iterations and the expertise of experienced designers. After completing these steps, the power- ground segments are adjusted to avoid obstacles during general signal routing.

Mesh Routing :

Power-Ground routing in state-of-art IC has mesh topology. There are five steps followed to create the topology.

1. Creating a Ring : 

A ring is built around the main part of the chip, and sometimes around specific sections. The ring's job is to link the power supply and any electrostatic discharge protection to the chip's overall power network. To keep resistance low, these connections, as well as the ring, are spread across multiple layers of metal. For instance, the ring might use metal layers from Metal2 to Metal8, skipping only Metal1.

2. Connecting I/O pads to the ring :

The top figure shows the connectors from the I/O pads to the ring. Each I/O pad has several metal layers with multiple fingers extending from it. These fingers should be connected as much as possible to the power ring to reduce resistance and improve the flow of current to the core.

3. Creating a Mesh :

A power mesh is made up of a series of stripes placed at specific intervals across two or more layers. The width and spacing of these stripes are determined by estimated power consumption and layout design rules. The stripes are arranged in alternating pairs, such as VDD-GND, VDD-GND, and so forth. The power mesh primarily uses the uppermost and thickest layers, while the lower layers have fewer stripes to prevent signal routing congestion. Stripes on neighboring layers are typically connected with as many vias as possible to reduce resistance.

4. Creating Metal1 rails :  

The Metal1 layer is where the power-ground distribution network connects to the design's logic gates. The width and spacing (current supply capability) of the Metal1 rails are usually defined by the standard cell library. The standard cell rows are arranged "back to back," allowing each power supply net to be shared between two adjacent cell rows.

5. Connecting the Metal1 rails to the mesh : 

Finally, the Metal1 rails are connected to the power mesh using stacked vias. A critical factor is ensuring the appropriate size of the via stack (i.e., the number of vias in the stack). Ideally, the most resistive part of the power distribution should be the Metal1 segments between the via stacks, rather than the stacks themselves. Additionally, the via stack is optimized to preserve the design's routing flexibility. For instance, depending on the direction of routing congestion, a 1x4 array of vias might be more effective than a 2x2 array.

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What is Floorplanning in VLSI Physical Design ?

Design Flow & Floorplanning :

Chip planning involves organizing large parts of a chip, Chip planning has three main stages: (1) floor planning, (2) pin assignment, and (3) power planning. 

 A gate-level or RTL netlist can be automatically divided into modules. These modules can also be taken from a hierarchical design. Large chip modules are arranged as blocks or rectangular shapes. Floor planning decides where these shapes go and their sizes, based on the areas and aspect ratios of the modules to optimize chip size, reduce interconnect, and improve timing. This stage ensures that every chip module is assigned a shape and a location. This facilitate gate placement and every pin that has an external connection is assigned a location so that internal and external nets can be routed. Pin assignment connects outgoing signals to block pins, and I/O placement finds locations for the chip's input and output pads, usually around the edge of the chip. This step ideally happens before floor planning, but locations can be updated during and after floor planning. Power planning creates the power supply network to ensure each block gets the right supply voltage. Partitioning and chip planning significantly impact later design steps.

Goals for Floorplan :

Importance of FLOOR PLAN:

- Arranging the partitioned blocks on a chip 

- Placement of the macros

- Specifying the location of the I/O pads

- Specifying the location and number of the power pads

- Deciding the type of power distribution.

The core of the chip is made up of one or more top level blocks). Core is is surrounded by a ring of pads. The design of the blocks and the arrangement of blocks and pads can affect the overall chip area (and hence the cost/yield).

A module becomes a rectangular block after it is assigned dimensions or a shape. These blocks can be either hard or soft. The dimensions and areas of hard blocks are fixed. For a soft block the area is fixed but the aspect ratio can be changed.

A floor planning usually includes following parameters : 

- the area of each module 

- all potential aspect ratios of each module 

- the netlist of all external connections incident to the module

Required Files for Floor Plan:

1. Synthesized Netlist :

A synthesised netlist describes the electrical connection of the ckt.. It consists of the electrical components and list of connected nodes. A synthesized Netlist can be written in Verilog/VHDL. 

2. Physical/Reference Library: 

Physical/reference libraries contains physical information for standard cell, macro cell and pad cells. These information are necessary for placement and routing.

3. Logic Libraries :

Logic library contains timing and functionality information of all standard cells used in the design. Timing information of hard macros such as IP, RAM, ROM etc also provided there.

4. Timing Constraints :

Design constraints, clock constraints, max skew, max and min insertion delay, number of clock domain,clock start point all these information are required.

5. Power Requirement : Power and ground Nets

6. Floor Planning Control Parameter : 

Die size estimation, core size, aspect ratio, core height, core width.

Optimization in Floor planning :

Area and shape of the global bounding box:  The global bounding box of a floor plan is the smallest rectangle that fits around all floorplan blocks. The area of this bounding box represents the total area of the top- level floorplan i.e. the full design and affects circuit  performance, yield, and manufacturing cost. To minimize the area of the global bounding box, we need to find the best (x, y) locations and shapes for each module so they fit closely together. Another goal, besides minimizing area, is to keep the aspect ratio of the global bounding box close to a target value. We can adjust the shapes of individual modules to achieve this. The area and aspect ratio of the global bounding box are connected, and both objectives are often optimized together.

Total wirelength: Long connections between blocks slow down signal propagation. For better performance connections must be shortened. Shorter connections means less wire capacitance i.e. reduced energy dissipation. Minimized wire length reduce power consumption. Shorter wire lengths improve routability and reduce manufacturing costs. If connections are too long or dense in one area, there may not be enough routing resources. Spreading circuit blocks apart can add routing tracks but increases chip size and cost. To simplify wire length calculation, we can connect all nets to the centers of the blocks. This method is accurate for small and medium blocks and allows quick interconnect evaluation.

Floorplan Tree :

A slicing floorplan is created by repeatedly dividing a  rectangular area, starting with the entire chip, into smaller rectangles using horizontal or vertical cuts. Its a binary tree with k leaves and k-1 internal nodes. Each leaf represents a block and each internal node represents a horizontal or vertical cut line. Each internal node has exactly two children.

A non-slicing floorplan cannot be formed by sequence of only vertical or horizontal cut in parent block. The smallest example of a non-slicing floorplan without wasted space is the wheel.

A floorplan tree represents a hierarchical floorplan. Each leaf node represents a block . Each internal node represent Horizontal Cut (H), Vertical Cut(V) or wheel (W). Order of Floorplan tree is the number of internal/non leaf node.

Constraint Graph Pair :

A constraint-graph pair is a floorplan representation that includes directed graphs showing the relationships between block positions. 

Two  types of graph :

1. the Vertical Constraint Graph , 

2. the Horizontal Constraint Graph

 A constraint graph consists of edges connecting n+2 weighted nodes, one source node s, one sink node t, n block nodes v1,v2 ….vn representing blocks m1,m2 ...mn. The weight of a block node represents the size of the corresponding block.  The weights of the source and sink node are zero.

Vertical Constraint Graph (VCG) node weights represent the heights of the corresponding blocks. Two nodes vi and vj with corresponding blocks mi and mj are connected with a directed edge from vi to vj if mi is below mj.

Horizontal Constraint Graph (HCG) node weights represent the widths of the corresponding blocks. Two nodes vi and vj with corresponding blocks mi and mj are connected with a directed edge from vi to vj if mi is to the left of mj.

Longest path in VCG is the min vertical extent requires to pack the blocks (floorplan height) 

Longest path in HCG is the min horizontal extent requires to pack the blocks (floorplan width)

A sequence pair is an ordered pair(S+, S-) of block permutations. Together the two permutations represent geometric relations between every pair of blocks a and b.

 If a appears before b in both S+ and S-, then a is the left of b.

 If a appears before b in S+ but not in S- then a is above b.

S+ : < ...a...b...> S- : <...a...b...> if block a is left of block b

S+ : < ...a...b...> S- : <...b...a...> if block a is above block b

Floorplan Sizing :

Floorplan Sizing determines the minimum area of floorplan as well as the associated orientations and dimensions of each individual block. Algorithm uses the shapes of both the individual blocks and top-level floorplan, shape functions and corner points (limits)play a major role in determining an optimal floorplan. Shape functions (shape curves) and corner points.

Floorplan sizing consists of three major steps:

1. Construct the shape functions of the blocks :

Before determining the shape of the top-level floorplan, we need to figure out the shapes of each individual block first, because the overall shape depends on them.  Shape function for two blocks are shown. The shape functions ha(w)  and hb(w) show the feasible height-width combinations of the blocks.

2. Determine the shape function of the top level floorplan:

The overall shape of the top floorplan is based on the shapes of the individual blocks. Combining the blocks in either a vertical or horizontal way can lead to different outcomes.

3. Find the floorplan and individual blocks dimensions and locations :

After figuring out the shape of the top-level floorplan, the smallest possible floorplan area is calculated. These minimum-area floorplans are always located at the corner points of the shape function. Once the corner point with the minimum area is found, we can determine the size and position of each individual block by tracing back from the overall floorplan's shape to each block's shape.

Linear Ordering – I , II & III :

Linear ordering algorithms are frequently used to generate initial placement solutions for iterative improvement placement techniques.  The goal of linear ordering is to arrange the given blocks in a single row to minimize the total wire length of the connections between them. 

New nets : have no pins on any block from the partially-constructed ordering

Terminating Nets : have no other incident blocks that are unplaced.

Continuing nets : have at least one pin on a block from the partially constructed ordering and at least one pin on an unordered block.

Gain of any block m is:                                                              gain(m) = no. of terminating nets of m – new nets of m

The block with the maximum gain is selected to be placed next.

There are 5 blocks A,B,C,D,E.

There are 6 nets N1, N2, N3, N4, N5, N6.

N1 = { A,B }              N2 = { A,D }

N3 = { A,C, E }         N4 = { B,D }

N5 = { C, D, E }        N6 = { D, E }

A is initial block. 

ITERATION - 0 :

ITERATION - 1 :

ITERATION - 2 :

ITERATION - 3 & 4  :

Initial & Final Arrangement:

Cluster Growth :

Floorplan is created by adding blocks one by one until all are placed. Start by choosing an initial block and placing it in any corner. Each new block is added and merged with the cluster, either horizontally or  vertically or  diagonally.  The position and orientation of each new block depend on the current cluster shape. The goal is to place blocks in a way that best meets the floorplan’s objectives. Only the orientations of individual blocks are considered. The order of adding blocks is determined by a linear ordering algorithm. Blocks are added in such a order that overall floor planning area is minimum.

Simulated Annealing :

Simulated annealing algorithms work by starting with an initial random solution and gradually improving it. In each step, they look at nearby solutions by making small changes to the current one and choose a new solution from these options. Unlike greedy algorithms, simulated annealing (SA) algorithms don’t always reject solutions that are worse than the current one.  In a greedy algorithm, if a new solution is better (for example, has a lower cost), it is accepted and replaces the current one. If no better solution is found nearby, the algorithm stops, as it’s stuck at a local minimum. The main problem with greedy algorithms is that they only accept changes that improve the solution. The idea of annealing can be used to solve complex optimization problems. In the case of minimizing costs, finding the best solution is like finding the lowest energy state of a material. Simulated annealing algorithms start with a messy (high-cost) solution and mimic the annealing process to create a more organized (lower-cost) solution. The simulated annealing algorithm is random by nature, so running it twice usually gives different results. The difference in outcomes comes from random decisions, like how new solutions are created (for example, by swapping parts) and whether those changes are accepted or rejected.

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What is Partitioning in Physical Design ?

In this article, we have thoroughly explored several critical aspects of partitioning in CMOS circuits. We began with a brief overview of partitioning, emphasizing its importance in the design flow. Next, we delved deeper into various levels and types of partitioning, highlighting why it is a crucial process. We also covered the fundamental rules of partitioning, drawing on graph theory to explain its principles. Additionally, we examined both pin and net-oriented netlists and concluded with detailed discussions on two different partitioning algorithms.

Design Flow and Partitioning:

VLSI design cycle is broadly categorized into Front End and Back End.  Front end starts with system specification. FE defines the logical behavior according the functional specifications. At the end of FE we get technology mapped gate level netlist. BE starts from there and main focus of BE is to translate the circuit we have got in FE into Silicon wafer with proper placement of blocks , essential power lines routing and etc. After all these the process lead to tape out. 

Partitioning is the initial step in the PD process.  Partitioning is dividing a chip into smaller blocks. Different functional blocks are separated and routing and placement is simplified. The designer breaks the larger design into various smaller  functional modules/blocks and then proceeds with implementation of these smaller modules during RTL design phase.  These smaller functional blocks are structurally instantiated or linked in the main module.  Main module is called TOP LEVEL module. This type of partitioning is called as Logical Partitioning.

What is Partitioning ?

To simplify complex integrated circuit designs, they are divided into smaller parts called modules. These modules can be as simple as a few electrical components or as complex as fully functional integrated circuits (ICs).  A tool called a partitioner splits the circuit into smaller subcircuits/ partitions/blocks. It aims to reduce the number of connections between these partitions while adhering to design rules like maximum size and delay limits. 

If each block is designed without considering the others, it can lead to problems. More connections between partitions can increase circuit delay and decrease reliability. Too many connections can create dependencies that slow down the design process. The main objective is to minimize connections between sub-circuits to improve performance and meet design constraints. Constraints may include limits on the logic size in a partition or the number of external connections (e.g., limited by the number of I/O pins on a chip). By following these points, designers aim to create efficient, reliable, and easily manageable integrated circuits.

Level of Partitioning :

Circuit Partitioning (CP) is an important task in VLSI design applications. Partitioning algorithms are used to achieve various objectives such as Circuit Layout, Circuit Packaging and Circuit Simulation.

Level Of Partitioning is as follows- 

1. System Level Partitioning :

A system is partitioned into group of PCBs. Each sub-

system can be designed as single PCB.

2. Board level partitioning :

A PCB is partitioned into sub- circuits. Each subcircuit

fabricated as VLSI Chips.

3. Chip Level Partitioning : Circuit assigned to the chip is

divided into manageable sub circuits.

Why Partitioning is Important?

1. Physical packaging : Partitioning decomposes the system in order to satisfy the physical packaging constraints. The partitioning conforms to a physical hierarchy ranging from cabinets, cases, boards, chips, to modular blocks.

2. Divide and conquer strategy : Partitioning helps manage complex designs by breaking them into smaller parts. Thisapproach allows team members to work on different sections, creates a logical order for design, converts the netlist into a physical layout for planning, assigns cells to specific areas for placement and RLC extraction, and coordinates between logic and layout for simulation.

3. System emulation & Rapid Prototyping : One way to emulate and prototype a system is by using FPGAs to build the hardware. Since FPGAs usually have less capacity than modern VLSI designs, these prototype systems use a hierarchical setup of multiple FPGAs. A partitioning tool is necessary to map the netlist onto the hardware.

4. Hardware & Software Codesign : For hardware and software codesign, partitioning is used to decompose the designs into hardware and software.

5. Management of Design Reuse : For huge designs especially system-on-a-chip, we have to manage design reuse. Partitioning can identify clusters of the netlist and construct functional modules out of the clusters.

Rules of Partitioning :

1. Interconnections between Partitioning: Reducing interconnections decreases delay and interaction between partitions, simplifying independent design and fabrication.

2. Delay Due to Partitioning: Partitioning a circuit may result in the critical path crossing between partitions multiple times.

3. Number of Terminals: The number of nets needed to connect a sub-circuit to other sub-circuits does not exceed the sub-circuit's terminal count.

4. Number of Partitions : A large number of partitions can simplify the design of individual sections, but it may also increase fabrication costs and the number of interconnections between partitions.

5. Are of each partition

After Circuit Partitioning :

- Area occupied by each partition is estimated

- Possible shapes of blocks can be ascertained

- Number of terminals required by each block is known

- Netlist specifying connections between block is available

Graph Theory & Partitioning :

Graphs are used in physical design algorithms to describe and represent layout topologies.

A graph G(V,E) is made up of two sets :

(1) Elements : Set of nodes or vertices denoted as V

(2) Edges : relations between the elements, denoted as E

A hypergraph consists of nodes and hyperedges. In a hypergraph, edges are sets of any number of vertices. Hyperedges are commonly used to represent multi-pin nets or multi-point connections within circuit. Hypergraph can be directed or non-directed.

Order of Hypergraph = Size of vertex set,

Size of Hypergraph = Size of the edges set

Pin & Net Oriented Netlist:

A netlist is a list that shows all the connections (nets) and the components they link together in a design. It can be organized in two ways:

(i) Pin-oriented: each design component has a list of associated nets

(ii) Net-oriented: each net has a list of associated design components

Netlists are created during logic synthesis and are a key input to physical design. A connectivity graph is a representation of the netlist as a graph. Cells, blocks and pads correspond to nodes, while their connections correspond to edges.

Partitioning Algorithm:

A cell is any logical or functional unit built from component. A partition or block is a grouped collection of components and cells. The k-way partitioning problem seeks to divide a circuit into k partitions. The most common partitioning objective is to minimize the number or total weight of cut edges while balancing the sizes of the partitions.  Often, partition area is limited due to packing considerations and other boundary conditions implied by system hierarchy, chip size, or floorplan restrictions.  Circuit partitioning, is very hard to solve. As the problem gets bigger, the time needed to find the best solution grows very quickly.  There is no known fast and perfect method to solve balance- constrained partitioning.

There are two types of partitioning methods:

1. Constructive or Iterative Method : A constructive algorithm creates a partitioning from the graph that represents the circuit or system. Iterative methods work to improve the quality of an already existing partitioning solution.

2. Deterministic or Probabilistic Method : Deterministic programs always produce the same solution each time they run. Probabilistic methods give different solutions each time because they use random numbers.

Methods, like the Kernighan-Lin (KL) algorithm and the Fiduccia-Mattheyses (FM) algorithm, can find good solutions and run relatively quickly. Optimization using simulated annealing can address particularly challenging partitioning problems.  KL algorithm is sensitive to the number of nodes and edges. The KL algorithm performs partitioning through iterative improvement steps.The KL algorithm is based on exchanging (swapping) pairs of nodes, each node from a different partition.

FM algorithm is sensitive to the number of nodes and nets (hyperedges). The FM algorithm is typically applied to large circuit netlists. This algorithm is more naturally applicable to partitions of unequal size or the presence of initially fixed cells. FM algorith offers best tradeoff between solution quality and runtime. 

Partition area is limited by packing considerations and other boundary conditions such as chip size, or floorplan restrictions. Commercial Tool uses command line options or a GUI to create and manage partitions. Changes the net-list tree structure to create hierarchy nodes at the top level that can be physically divided. This ensures that the nodes are evenly sized and reduces the number of top-level connections needed for the hierarchy blocks. Finds the best way to divide a design into blocks that can be worked on separately. Makes sure the partitions are balanced by size or number of instances. Reduces the number of top-level connections between block I/O ports. Ensures the netlist is partitioned without changing how it works.

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