What is Placement in VLSI Physical design?

Design Flow & Placement:

In the VLSI design flow, placement is a crucial step in the physical design. It comes after Partitioning and Floor planning. Logic Synthesis converts a high-level RTL design into a netlist of gates and cells. Partitioning divide the larger design into smaller modules. Floor planning allocates general areas for major components and defines regions for standard cells, macros, pin assignment allocates input/output (I/O) pins. Placement is the process of determining the optimal locations for standard cells, macros, and other modules within a chip’s layout. It aims to achieve the best balance between performance, power, and area (PPA) while minimizing wire length, congestion, and delays. 

Placement Phases: There are 2 placement phases in PD. 

(1) Global Placement : Provides a rough layout of the cells and modules to minimize wire length and congestion. Focuses on overall optimization but allows overlaps between cells.

(2) Detailed Placement : Adjusts the positions to remove overlaps and ensure cells are aligned with legal sites or predefined rows on the chip. Minimizes wire length deviations introduced during legalization. 

After placement, the routing phase connects all components with metal wires, finalizing the design's physical layout.

Objective & Challenges of Placement:

Placement is a critical step that transforms a logical design into a physically realizable layout. It ensures that the layout is timing-efficient, power-optimized, and routable, forming a bridge between logic synthesis and routing in the IC design flow.

# Placement Constraints and Objectives:

(1) Minimize Wire length : Shorter wires reduce signal delays and improve performance.

(2) Timing Closure : Placement must ensure paths meet the required timing.

(3) Power Optimization : Efficient placement helps reduce dynamic and leakage power.

 

(4) Congestion Control : Placement must prevent routing congestion to ensure the design is routable.

# Challenges in Placement :

(1) Handling Large Netlists: Efficiently placing millions of cells

(2) Preventing Overlaps: Global placement often creates dense clusters that need to be legalized.

(3) Timing vs. Wire length Trade-offs : Minimizing wire length can sometimes degrade timing performance, and vice versa.

(4) Macro Handling: Large blocks (macros) need special consideration to avoid placement gaps and routing blockages.

Different Types of Placement :

Optimization in Placement:

In placement, the optimization objectives focus on achieving high performance, low power consumption, and manufacturability.

1. Wire length Minimization :

Objective: Reduce the total wire length to lower signal propagation delays, power consumption, routing congestion.

Impact: Reducing wire length improves timing (faster circuits) and reduces the likelihood of routing congestion.

2. Overlap Minimization :

Objective: Ensure that no two cells overlap after placement, especially during the detailed placement phase.

Impact: Non-overlapping placement improves routability and allows legalization (alignment with power rails).

3. Timing Optimization :

Objective: Minimize signal delays by reducing interconnect delays that affect the overall clock cycle.

Impact : Enhances the performance of the circuit by ensuring faster data propagation through critical paths.

4. Row Length Equality :

Objective: Ensure equal row lengths during standard-cell placement to avoid inefficient use of layout space.

Impact: Uniform rows prevent area wastage and ensure even wire distribution, reducing routing congestion.

5. Congestion Minimization :

Objective: Avoid high-density areas where wiring overlaps or routing resources become constrained.

Approach:

(i) Spreading cells: Cells are distributed more evenly by scaling their positions and moving them out of dense regions.

(ii) Congestion-aware placement: Similar to density estimation, routing congestion is estimated on a grid to guide placement.

Impact: Reducing congestion ensures routability and avoids post-routing failures.

6. Power Optimization:

Objective: Minimize the power consumed by interconnects and switching activities.

Approach:

(i) Reduce wire length to lower dynamic power (caused by signal switching across long nets).

(ii) Place high-activity cells closer to minimize interconnect delay and energy consumption.

Impact: Leads to low-power designs, which are essential for battery-powered devices.

7. Legalization:

Objective: Align cells to discrete rows and ensure legal locations after global placement.

Approach:

(i) Snap cell coordinates to grid points that correspond to power rails.

(ii)Optimize wire length and overlap during incremental legalization.

Impact: Produces valid placements that meet manufacturing requirements w/o overlaps/misplaced cells.

8. Temperature-Based Optimization (Annealing):

Objective: Use simulated annealing to explore various placements and escape local minima in the optimization process.

Impact: Aims for a global optimum solution by balancing interconnect minimization and overlap reduction as the temperature decreases.

These objectives collectively ensure that the chip layout achieves high performance, efficient power usage, low congestion, and manufacturability. Different algorithms may emphasize some objectives over others based on design constraints and priorities.

Modern Placement:

Modern placement in EDA refers to advanced methods which combines mathematical optimization, multi-objective considerations, and sophisticated algorithms to address the demands of current chip designs, balancing efficiency, scalability, and performance while considering design constraints, including wire length, timing, power, and congestion. # Key Aspects of Modern Placement:

1. Multi-Objective Optimization: Modern placement aims to optimize multiple goals at once, like shortening wire length, saving power, managing heat, improving timing, and easing routing. This approach is key for high-performance, power-efficient chip designs.

2. Analytic and Force-Directed Methods: Analytic Methods: These use mathematical models like quadratic and nonlinear optimization to approximate interconnect lengths and solve placement as an optimization problem. Quadratic methods are popular due to their computational efficiency, while nonlinear methods provide better accuracy for designs with various component sizes. Force-Directed Methods: Here, cells are treated as objects subject to attractive and repulsive forces. Attraction represents connectivity, by closely connected cells to move closer, and repulsion prevents overlapping by spreading cells apart.

3. Hierarchy and Clustering Techniques: To handle large-scale designs, modern placement algorithms use clustering, which groups highly interconnected cells together in early stages. This reduces the complexity of initial placement and allows for more efficient optimization. After clustering, cells are progressively "un-clustered" and refined in stages, allowing for scalable placement even with millions of components.

4. Legalization and Detailed Placement: Legalization ensures that cells are moved to exact, non-overlapping legal positions, typically aligning with a grid, while minimizing disturbance to the global placement. Detailed Placement then fine-tunes cell positions to reduce minor overlaps and improve wire length and timing by making small local adjustments.

Min-cut Placement :

Min-cut placement is a method in chip design where a circuit's layout is divided or partitioned repeatedly into smaller regions to minimize the number of connections or cuts between these regions. The aim is to balance the number of components in each region while reducing the connections that cross boundaries, which helps minimize wire length and improves timing. Min-cut placement effectively balances components and reduces interconnections, laying a foundation for efficient routing and timing optimization in later stages.

# How min-cut placement generally works:

1. Partitioning: The design area is repeatedly split into smaller sections, each with about the same number of cells. During each split, an algorithm picks a dividing line and tries to keep closely connected parts on the same side to reduce the number of connections crossing the line.

2. Objective: The main objective is to minimize the number of "cuts" or interconnections between partitions, as these inter-partition connections can lead to longer wires and increased delay.

3. Balancing Cells: Min-cut placement also strives to balance the number of components in each partition. This balancing is important because it prevents one area from becoming congested while another has unused space.

4. Hierarchical Refinement: Min-cut placement is a hierarchical approach. Each sub-region is further divided until each partition is small enough that detailed placement techniques can be applied to finalize the exact locations of cells within each region.

5. Advantages and Applications: Min-cut placement is well-suited for large designs and can handle hierarchical structures efficiently. Tools like Capo, which is a popular min-cut placer, are used to achieve routable placements, especially in designs with high density and many fixed obstacles.

# There are 2 approaches to divide the layout :

1. Alternating Cutline Directions :

Alternating cutline Directions is a technique in partition-based placement where the direction of cutlines alternates between horizontal and vertical during recursive partitioning. The design area is split into regions, ensuring a balanced distribution of cells in both axes. By alternating the cutline direction, the method avoids skewness, maintains compact layouts, and reduces wire length. Closely connected components are grouped to minimize routing congestion. This structured placement simplifies later stages, like legalization and optimization. It is especially effective for large, complex circuits with dense interconnections.

2. Repeating Cutline Directions :

Repeating Cutline Directions is a technique in partition-based placement where the same cutline direction (horizontal or vertical) is used repeatedly during multiple levels of recursive partitioning. This approach divides the design area into increasingly smaller regions along a single axis, creating elongated partitions in one direction. It may simplify some placement strategies but risks uneven distribution, potentially increasing wire length and routing congestion. Repeating cutline directions can be suitable for designs with specific constraints, like high connectivity along one axis. However, it is less commonly used compared to alternating cutline directions due to its limitations in achieving balanced layouts.

Analytic Placement :

Analytic placement is a technique in chip design that uses mathematical optimization methods to determine the locations of circuit components on a chip. The goal of analytic placement is to minimize an objective function, usually related to the circuit’s performance, such as total wire length/delay, by treating the placement problem as a mathematical optimization task.

# Key Aspects of Analytic Placement:

1. Optimization-Based Approach: Analytic placement relies on mathematical optimization methods like numerical analysis or linear programming. Unlike heuristic methods, it formulates placement as an objective function and seeks to find the optimal configuration of cells to minimize this function. The approach involves treating placable objects (like cells) as dimensionless points initially, which simplifies the mathematical calculations.

2. Objective Functions: The most common objective function in analytic placement is wire length minimization, often using a quadratic function (squared Euclidean distance) to approximate the total wire length. Quadratic wire length models make it easier to apply mathematical techniques, but other functions, such as nonlinear ones, may be used for greater accuracy. In addition to wire length, other objectives like minimizing circuit delay, reducing congestion, or achieving better timing are sometimes considered.

3.Two Main Stages: Global Placement: This is the first stage, where cells are positioned to minimize the objective function across the entire layout. At this stage, overlaps are allowed, and cells may form clusters. Detailed Placement: In the second stage, cells are moved slightly to remove overlaps and achieve legal positions while keeping the objective function optimized.

4. Convex Optimization and Convexity: In quadratic placement, the placement problem often becomes a convex quadratic optimization problem. Convexity ensures that any local minimum solution is also a global minimum, making it possible to solve the problem efficiently by setting the partial derivatives of the objective function to zero.

5. Additional Techniques for Spreading: After the initial analytic placement, cells may be too close to each other, creating overlaps. Dedicated techniques like cell spreading are applied to ensure non-overlapping placement. This involves redistributing cells to avoid congestion while preserving the optimization of the objective function.

6. Types of Analytic Placement:

Quadratic Placement: Uses a quadratic cost function, which emphasizes minimizing longer connections. Quadratic placement is efficient and scalable.

Nonlinear Placement: Uses more complex, nonlinear functions to represent interconnects, providing better accuracy, especially for components with diverse sizes, but it can be computationally slower than quadratic methods.

# Advantages and Limitations:

Advantages: Analytic placement is systematic, scalable, and provides highly optimized results for wire length and other performance metrics. It is also suitable for very large designs due to its mathematical rigor.

Limitations: Analytic methods may require complex handling for real-world design constraints, such as routing congestion or timing requirements. Some methods, particularly nonlinear optimization, can be slower and require careful tuning for stability.

Analytic placement is widely used in EDA tools because it provides an efficient, scalable way to produce high-quality placements that lay the foundation for effective routing and timing optimization.

# Why Analytic Placement Matters ?

As chip designs grow increasingly complex, the need for precise and efficient placement methods has never been greater. Analytic placement provides the mathematical rigor and computational power needed to meet modern design requirements, ensuring faster, smaller, and more power-efficient chips. With its blend of theoretical elegance and practical impact, analytic placement remains a cornerstone of VLSI design, driving innovation in one of the most challenging engineering domains.

Simulated Annealing :

Simulated annealing is a heuristic optimization technique used in placement algorithms, particularly in the global placement phase of VLSI design. It mimics the physical process of annealing in metallurgy, where materials are slowly cooled to minimize internal energy and achieve a stable configuration. The following are key aspects of simulated annealing placement:

# Basic Principles :

1. Cost Function:

- Placement quality is evaluated using a cost function, which combines factors.

- Wirelength: Often computed using the half-perimeter wirelength (HPWL) metric.

- Cell Overlap: Quantifies overlaps between cells, penalizing large overlaps more heavily.

- Row Inequality: Penalizes deviations in row lengths, which could cause inefficiencies

2. Cooling Schedule:

- The process starts at a high temperature, allowing more random placement changes.

- As the temperature decreases, the algorithm becomes less tolerant of changes that increase cost.

- The temperature is reduced gradually using a cooling factor, alpha, which may vary during the process:

(a) Initial Phase: High cooling rate e.g., alpha = 0.8 to explore configurations broadly.

(b) Middle Phase: Slower cooling e.g., alpha = 0.95 for fine-tuning.

(c) Final Phase: Rapid cooling alpha = 0.8 for convergence.

# Algorithm Steps:

1. Initialization: Begin with a high temperature and a random initial placement of cells.

2. Placement Perturbation: Modify the placement by moving or swapping cells to generate new configurations.

3. Cost Evaluation: Calculate the cost of the new placement. If the new cost is lower, accept the change. If the cost is higher, accept the change with a probability based on the current temperature and cost difference.

4. Iterative Cooling: Reduce the temperature and repeat the perturbation and evaluation steps until the system "freezes" (temperature reaches a minimum threshold).

5. Equilibrium: At each temperature level, the algorithm runs enough iterations to achieve equilibrium, ensuring stability before cooling further.

# Applications : Effective for standard-cell placement, in designs with constraints like limited feed through cells/uneven layouts.

# Advantages:

1. Flexibility in handling complex cost functions.

2. Ability to escape local minima by accepting worse solutions at higher temperatures.

# Challenges:

1. Computationally intensive due to the large number of iterations.

2. Parameter tuning (e.g., cooling schedule, acceptance ratio) requires expertise.

# Example Tool : TimberWolf

1. A popular placement tool using simulated annealing.

2. Incorporates detailed cost functions and strategies for cell spreading, overlap minimization, and optimization of wiring directions.

3. This method is a robust approach for achieving high-quality placements in the design of integrated circuits.

Global Placement :

In Global placement components like cells and circuit modules are assigned approximate locations across the layout area. The primary goal at this stage is to minimize a cost function, related to wire length or timing constraints, without enforcing exact legal positions or preventing overlaps.

1. Optimization without Exact Positions: Components are placed to minimize interconnect length and congestion, but positions are not finalized.

2. Independent x and y optimization: Placement simplifies the process by optimizing cell locations separately along x, y axes.

3. Use of Mathematical Models: Quadratic or nonlinear models are used to achieve optimal placement.

4. Preliminary Layout: Provides a rough layout, leaving exact, overlap-free positions for detailed placement.

5. Foundation for Legalization: Serves as a starting point for legalization and detailed placement to finalize a feasible and efficient layout.

6. Global placement is crucial for creating an efficient starting point for further optimizations that lead to a functional and high-performance chip layout.

Legalization :

Legalization is a process that adjusts the positions of circuit components/cells on a chip layout to ensure they meet specific physical design constraints.

After the initial/ global placement, components may not align to designated legal positions, such as rows or grid points, and may even overlap. Legalization corrects these issues by moving cells to valid positions while minimizing disruption to the optimized layout.

# Key Aspects of Legalization:

1. Aligning to Legal Positions: Cells are moved to specific legal sites, often aligning with power rails or rows. This ensures that the design complies with the manufacturing requirements, which mandate cells to be placed at predefined locations to ensure proper connections and spacing.ns to ensure proper connections and spacing.

2. Removing Overlaps: During global placement, cells may be placed too close to each other, creating overlaps. Legalization removes these overlaps by shifting cells slightly, while trying to maintain the overall structure and objective of the initial placement.

3. Minimizing Disturbance: Legalization aims to make only minimal adjustments to the positions of cells to preserve the optimized parameters like wire length or timing achieved during global placement. Excessive movement can increase wire length, affect timing, and create new congestion, so algorithms are designed to balance legality with minimal disruption.

4. Handling Physical Constraints:

Legalization accounts for physical design constraints, such as spacing rules, row alignment, and fixed cell locations. It also adapts to different sizes of components, including standard cells and larger macro blocks.

5. Legalization Algorithms:

Common algorithms for legalization include:

(i) Greedy Algorithms: Quickly place each cell in the nearest legal position, but may need refinement for optimal results.

(ii) Sliding Window or Branch-and-Bound: Works by reordering and slightly shifting cells within a defined window to achieve legal placement.

(iii) Dynamic Programming and Linear Programming: These techniques offer more systematic approaches to legalizing placements, especially for complex layouts with mixed cell sizes.

6. Integration with Detailed Placement:

Legalization is often followed by detailed placement, a fine-tuning stage where small adjustments further optimize the layout to improve performance metrics, such as reducing wire length or improving timing.

# Importance of Legalization:

Legalization is critical because it ensures the layout complies with all physical design rules and manufacturing constraints while retaining as much of the optimization from global placement as possible. This step is necessary before routing, as a legalized layout provides a reliable foundation for connecting the components without further conflicts or overlaps.

Detailed Placement :

Detailed placement follows global placement and legalization. During detailed placement, the precise positions of circuit cells are fine-tuned to improve design metrics like wire length, timing, power, and congestion. This stage aims to enhance the quality of the initial placement by making minor adjustments to cell positions without violating legal constraints by avoiding overlaps and maintaining alignment to rows.

# Key Aspects of Detailed Placement: 1. Fine-Tuning Cell Positions: Detailed placement fine-tunes the global placement layout by making minor, localized adjustments to enhance design quality while staying close to the original configuration. 2. Optimizing Wire length and Timing: The main goal of detailed placement is to minimize wire length, reducing delays and improving timing, especially along critical paths. 3. Congestion and Density Management : Congestion arises from densely packed cells, causing routing issues. Detailed placement algorithms spread cells to ease routing and prevent hotspots. 4. Improvement Techniques: Cell Swapping: Exchanging the positions of neighboring cells to reduce wire length or improve timing. Cell Sliding and Shifting: Adjusting cells slightly within rows or gaps to optimize spacing and align with power rails or tracks. Group Movement: Moving groups of cells within a sliding window to improve alignment and reduce wire length.

5. Window-Based Optimization: Detailed placement is often performed within small, localized windows or regions to reduce computational complexity and allow more focused optimization. The algorithms may reorder cells within these windows to minimize disruption to the overall placement.

6. Handling Unused Space: If there is unused space between cells in a row, detailed placement may shift cells slightly to either side or distribute them evenly, ensuring that no gaps lead to wasted area.

7. Ensuring Legalized Placement: Detailed placement adheres to legal positions determined during legalization, maintaining cell alignment and spacing to prevent design rule violations.

# Importance of Detailed Placement:

Detailed placement is crucial because it provides the final adjustments needed to optimize performance metrics before the routing stage. By fine-tuning the positions of cells, detailed placement improves wire length, timing, and congestion, resulting in a more efficient and high-performing chip layout.

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PIn Assignment & Power-Ground Routing in Physical Design

 

Design Flow and Pin Assignment :

When planning the layout of large blocks, where you place the connection points (terminals) is very important. These connection points, called I/O pins, are usually placed on the edges of the blocks to keep the wiring short. The best spots for these pins depend on how the blocks are arranged. During pin assignment, each signal (net) is assigned a specific pin location to improve the overall design. The main goals are to make sure the wiring is easy to route and to reduce unwanted electrical effects both inside and outside the block. The objective of external pin assignment is to link each incoming or outgoing signal to a unique I/O pin. After assigning each necessary net to its designated pin, the connections must be optimized to minimize wire length and reduce electrical parasitics, such as coupling or signal integrity loss.

More on Pin Assignment :

Pin assignment is used to connect cell pins that are functionally or electrically equivalent, such as during standard cell placement. Two pins are considered functionally equivalent if swapping them does not alter the design's logic, and they are electrically equivalent or equi-potential if they are connected. The primary goal of internal pin assignment for cells is to minimize congestion and reduce interconnect length between cells.  The pin assignment techniques described below are applicable to both chip planning and placement stages.

Pin Assignment using Concentric Circles :

The algorithm connect a block to all its associated pins in other blocks with minimum of cross-connections. It operates under the assumption that all outer pins have fixed positions. Inner pins are positioned based on the locations of their electrically equivalent outer pins. The algorithm employs two concentric circles: the inner circle for the pins of the block being considered and the outer circle for pins in other blocks. The primary goal is to assign valid pin locations on both circles w/o no net overlap.

1. Determine the Circles : 

The two circles are drawn such a way that all pins that belong to the block are outside the inner circle and all external pins are outside the outer circle.

2. Determine the Points :

For each point, draw a line from that point to the center of the circles. Then, move each outer point to where the line meets the outer circle, and move each inner point to where the line meets the inner circle.

3. Determine Initial Mapping : 

The initial setup pairs each outer pin with a matching inner pin. Start by choosing any pin and assign it to an inner pin. Then, assign the rest of the pins either in a clockwise or anti-clockwise direction.

4. Optimizing the Mapping :

Repeat the process of pairing outer and inner points in different ways. Start with the same outer point, but try pairing it with different inner points, and then pair the rest of the points accordingly. Continue until all possible pairings have been tried. The best pairing is the one that has the shortest total distance between the points. In this problem, an example pairing is shown on the left, the best pairing is in the center, and the final pin assignments are on the right.

Topological Pin Assignment :

This algorithm is an improvement to concentric-circle pin assignment algorithm. It takes into account external block positions and multi -pin nets. This allowed pin assignment even when external pins are behind other blocks. This algorithm is an improvement to concentric-circle pin assignment algorithm. It takes into account external block positions and multi -pin nets. This allowed pin assignment even when external pins are behind other blocks.

This method allows multiple block to be considered simultaneously. There are two blocs a & b. On block a, consider the midpoint lines lm~a and lm~b. The point d1 is formed because it is the farther point on lm~a. The point d2 is formed because it is closer point on lm~b.  The point d3 is formed because it is the farther oint on lm~b. Using d1-d3, the pins are “unwrapped” accordingly when projected onto m’s outer circle.

Design Flow : Power & Ground Routing :

Chip planning involves designing the power-ground distribution network and positioning supply I/O pads or bumps. Up to 20-40% of all metal resources on the chip are used to supply power (VDD) and ground (GND) nets.

The power planning process includes iterative steps such as:

1. Early simulation of major power dissipation components.

2. Initial estimation of overall chip power.

3. Analysis of total chip power and peak power density.

4. Examination of total chip power fluctuations.

5. Analysis of inherent and additional fluctuations caused by        clock gating.

6. Early analysis of power distribution, including average, maximum, and multi-cycle fluctuations.

Design of a Power-Ground Distribution :

Every cell needs both VDD and GND connections. They connect each cell in the design to a power source. VDD and GND supply lines are large, cover the entire chip, and are routed before any signal lines. Core supply lines differ from I/O supply lines, which usually have a higher voltage. Single core power line and core ground line are often enough, For some ICs, like mixed-signal or low-power designs, may have multiple power and ground lines. Routing power/ground lines is different from routing signal lines. Power/ground lines require their own metal layers to avoid taking up space needed for signal routing. Thicker metal layers, typically the top two in the manufacturing process, are preferred for power and ground lines due to their lower resistance. When the power-ground network spans multiple layers, sufficient vias must be used to carry current and prevent reliability issues like electro-migration. Supply lines carry high current, so they are often much wider than signal lines. The width of each wire segment can be adjusted based on the expected current. Wider segments have lower resistance, which reduces voltage drop. 

 There are two main approaches to designing power-ground distribution:

1. The planar approach : used in analog or custom blocks.

2. The mesh approach : more common in digital ICs.

Planar Routing:

Power supply nets can be routed using planar routing when 

(1) only two supply nets are present in the design,

(2) a cell needs a connection to both supply nets.

A Hamiltonian path is created that connects all the cells. The path divides the layout into two regions: one for each supply net. Each supply net is routed either the left/right side of the path for each cell. So both supply nets can be laid out without conflicts in across the design.

Routing the power and grounds nets and grounds nets in this planar fashion can be accomplished with the following three steps:

1. Planarize the topology of nets:

Since both power and ground nets must be routed on the same layer, the design should be divided using a Hamiltonian path. Start routing the power and ground nets from the left and right sides, respectively. Ensure both nets expand in a tree-like structure,  avoiding overlap and maintaining separation by the Hamiltonian path. The precise routing will depend on the pin locations. Connect the cells wherever a pin is encountered during the routing process.

2. Layer Assignment :

Net segments are allocated to specific routing layers considering factors such as routability, the resistance and capacitance characteristics of each available layer, and design rule constraints.

3. Determining the widths of the net segment:

The width of each segment is based on the maximum current it needs to carry. This width is determined by summing up the currents from all the connected cells, according to Kirchhoff's Current Law (KCL). For large currents, designers often increase the width by stacking multiple layers vertically, connected by vias. Deciding the right width is usually an iterative process because currents are influenced by timing and noise, which are, in turn, affected by voltage drops, creating a cyclic dependency. This loop is typically resolved through multiple iterations and the expertise of experienced designers. After completing these steps, the power- ground segments are adjusted to avoid obstacles during general signal routing.

Mesh Routing :

Power-Ground routing in state-of-art IC has mesh topology. There are five steps followed to create the topology.

1. Creating a Ring : 

A ring is built around the main part of the chip, and sometimes around specific sections. The ring's job is to link the power supply and any electrostatic discharge protection to the chip's overall power network. To keep resistance low, these connections, as well as the ring, are spread across multiple layers of metal. For instance, the ring might use metal layers from Metal2 to Metal8, skipping only Metal1.

2. Connecting I/O pads to the ring :

The top figure shows the connectors from the I/O pads to the ring. Each I/O pad has several metal layers with multiple fingers extending from it. These fingers should be connected as much as possible to the power ring to reduce resistance and improve the flow of current to the core.

3. Creating a Mesh :

A power mesh is made up of a series of stripes placed at specific intervals across two or more layers. The width and spacing of these stripes are determined by estimated power consumption and layout design rules. The stripes are arranged in alternating pairs, such as VDD-GND, VDD-GND, and so forth. The power mesh primarily uses the uppermost and thickest layers, while the lower layers have fewer stripes to prevent signal routing congestion. Stripes on neighboring layers are typically connected with as many vias as possible to reduce resistance.

4. Creating Metal1 rails :  

The Metal1 layer is where the power-ground distribution network connects to the design's logic gates. The width and spacing (current supply capability) of the Metal1 rails are usually defined by the standard cell library. The standard cell rows are arranged "back to back," allowing each power supply net to be shared between two adjacent cell rows.

5. Connecting the Metal1 rails to the mesh : 

Finally, the Metal1 rails are connected to the power mesh using stacked vias. A critical factor is ensuring the appropriate size of the via stack (i.e., the number of vias in the stack). Ideally, the most resistive part of the power distribution should be the Metal1 segments between the via stacks, rather than the stacks themselves. Additionally, the via stack is optimized to preserve the design's routing flexibility. For instance, depending on the direction of routing congestion, a 1x4 array of vias might be more effective than a 2x2 array.

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