Buried Power Rail

Belgium based IMEC  has announced functioning devices using a new technique of burying power rails below active devices. Is this technique effective in addressing power rail congestion issues prevalent in state-of-art devices. Buried power rail is usually referred as BPR. Its is a new topic and before diving deep into it, lets’s start with some definitions :

1. What is a power rail ?

Power rail can be defined as the voltage source within the device from which its various functions can draw power.

2. What is routing congestion in VLSI?

When the number of routing tracks available for routing in a given location is less than the number necessary, the area is considered congested and hence, is termed as congestion in VLSI Physical Design Flow. The number of nets that may be routed through a given region will be limited.

3. Now What is a buried power rail?

A buried power rail is a power rail found inside the semiconductor substrate instead of on a metal layer. The rail itself is constructed to run underneath the active layer where semiconductor components are found (i.e. transistors and diodes).

IMEC is Interuniversity Microelectronics Centre. Its an international research & development organization, active in the fields of Nano Electronics and digital technologies. Their headquarter is in Belgium. In 2019 IMEC first announced about BPR and continuously working on that. In 2021, IMEC for the first time showed backside connectivity through nTSVs landing on metal-1 pads in the wafer’s front side. In 2022 , IMEC has presented the first experimental demonstration of a routing scheme for logic ICs with backside power delivery enabled through nano-through-silicon-vias (nTSVs) landing on buried power rails (BPRs). The BPRs connect to scaled FinFET devices and their performance was not impacted by backside wafer processing. Since IMEC’s first announcement in 2019, different implementations have been proposed.

Designing semiconductor devices presents a whole range of different challenges including quantum tunneling, causing current leakage, overheating devices, propagation delay, and feature sizes. Once the active components of a semiconductor are designed (i.e. transistors), the remaining layers are used to route signals and power. This stage is very similar to routing a PCB, and as such can suffer from similar problems.

Generally, routing power rails is the last step in a design as routing signals takes priority (especially in high-frequency circuits), and as such is given the topmost layer (called M1). As a result, power rails can be far from their active components while the use of many interconnects introduces resistance, inductance, and reflections.

IMEC demonstrates FinFET CMOS with Buried Power Rails.The demonstration utilises FinFET CMOS to show that buried power rail (BPR) technology can work with modern technologies.A paper was published in 2019 by a group of researchers from ARM and IMEC on this topic. In this paper researchers showed that buried rails with front-side power delivery system could improve the worst-case IR drop from 70mV to 42mV (~1.7X reduction) whereas buried rails with back-side power delivery substantially reduce IR drop to 10mV (a 7X reduction).One of the concerns of using BPR technologies in semiconductor devices is the active layer's interference when embedding BPRs. Since the layer sits below the active layer, and these layers are created one after the other, there is a chance that device performance can worsen as a result of stress, degradation, and metal contamination. However, the demonstration by IMEC shows that these worries can be avoided to create fully-functional active devices down to the 3nm scale. The BPRs developed by IMEC are made from Tungsten (W), and via interconnects to this layer used Ruthenium (Ru). The effectiveness of the BPRs was further displayed after 900 hours of continual use at 330°C at a current of 4MA/cm2 with no electromigration failures being observed.

After discovering that the BRPs are made of tungsten, the question of resistance immediately comes to mind. Copper is a highly conductive element, and as such has a low resistance, but tungsten has a resistance almost four times higher than copper. As such, tungsten rails would have an additional power loss of 4 times that of copper, and therefore 4 times greater energy loss.

However, while tungsten may have a greater resistivity than copper, using BRPs provides advantages not possible with M1 power routing. Routing power rails below the active layer offers a shorter routing distance between active devices and power rails (remember that CMOS technology requires a direct connection to power rails VDD and VSS). As such, the total length of wire between the power and individual active devices is reduced.

The second advantage is that designers are given more freedom on routing layers by moving power routing below the active devices. As such, signal connections can be reduced in length which allows for greater speed of operation. A secondary study on BRPs has confirmed such advantages and has stated that grid power distribution can improve SRAM by 28.2%.

Buried Power Rails are still in development, and add an entirely new production step to a semiconductor. But their advantages are clear with reduced power rail length, improved efficiency, and a more compact design.

In the current technology scaling paradigm, semiconductor device physics and conductor parasitics are fundamentally limiting microprocessor performance beyond the 5nm process node. Many experiments showed promising returns from BPR and back-side power delivery. However, there are a number of designs, manufacturing technology, and packaging complexities need to be addressed and resolved before it is possible to fully enable back-side power delivery with BPRs for wide-spread industry adoption.

Video on this topic is here : 

Courtesy : Photo by Laura Ockel on Unsplash

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Nano Sheet FET (NSFET)

  Fig 1 : Different Types of FET

For last few decades VLSI industry has kept pace with Moore’s law and transition from one node to another happened. As the node proceeds designers were able to produce faster, more powerful, more energy-efficient microchips.This constant advancement has fueled advances in everything from cloud computing to smartphones, virtual reality to robotics, and additive fabrication to the Internet of Things (IoT). But as the cost and complexity of each new process node has continued rising, advances have slowed noticeably, despite the fact that there are applications such as AI and machine learning, big data analysis and data center servers that require the latest and most powerful CMOS solutions.
FET was introduced in 1959 and from then FET has been mostly built in the plane of the silicon. In 2012, at 20nm, the industry made the first transition from “planar” MOSFETs to fin field-effect transistor (FinFET) architectures to maintain the Moore’s Law scaling path. In a FinFET, the channel between source and drain terminals is in the form of a fin and the fin is contacted on three sides by the gate. This structure provided better control of the channel formed within the fin. As a result, FinFETs helped significantly with current leakage. Since then, fin height has been increased to obtain a higher device drive current at the same footprint. Today's designs place the gate stack directly above the channel area. One problem is that as these structures become smaller, it becomes more difficult to block the charge leak across the transistor. With FinFETs, the gate surrounds the rectangular silicon fin on three sides, leaving the bottom side connected to the body of the silicon. This allows some leakage current to flow when the transistor is off. The resulting leakage leads to hotter, less power-efficient microchips. As scaling is pushed beyond 5nm, the FinFET road-map seems to be coming to an end . The initial technology beyond the FinFET will be the stacked Nano Sheet transistor. This is broadly part of a concept that may also be described as gate all around or GAA transistors, which address several challenges around FinFETs for the 3nm node and beyond, promising performance boosts of more than 25 percent and power consumption reductions of more than 50 percent. Instead of using a stack of Nano Wires to bridge the source and drain, a stack of thin sheets of silicon is utilized. Unlike FinFET technology, in Nano Sheet technology the gate surrounds the channel region in its entirety, providing even better control of current leakage. This stacked structure supports far more advanced semiconductor fabrication processes, including a channel region that is tilted upward to create a wider path for current. In Nano Sheet FET the channel region consists of multiple, horizontal, nanometer-thin sheets stacked atop one another. A gate fully wraps around the channel to provide better channel control compared to a multi-gate FinFET with limited additional process complexity.

                       Fig 2: Cross Section of FETs

One of the key advantages of a Nano Sheet device is its short channel control, which is critical to threshold voltage variation (Vth). Smaller Vth variation is crucial for good device. Nano sheets offer excellent electrostatics and short channel control, and can be fabricated with minimal deviation from FinFET. On the other hand, multiple Vth here comes with more restrictive requirements on dimensions (because of limited-sheet-to-sheet space). Still, researchers have demonstrated nanosheet transistors with more than 50 percent lower Vth variations.
Key advantages of Nano Sheet FET over FinFETs includes design flexibility like adjusting the effective width of the transistor channel. More width means you can drive more current and switch a transistor on and off more quickly. These sheets can be made wide to boost current, or narrow to limit power consumption. For example, a Nano Sheet with a wider sheet provides more drive current and performance. A narrow Nano Sheet has less drive current, but takes up a smaller area.
Not all chips currently being produced require FinFETs. Analog, RF and other components are built around more mature processes and are still in high demand. FinFETs will still be viable for chips from 16nm to 5nm, while planar transistors will remain the mainstream technology at 22nm and above.

Fig. 3: Technology nodes over the past and prospective vision for future

The adoption of nano-sheet FET should follow the adoption of FinFET with a 10-years shift. Is it anticipated that the 3-nm node will announce the start of a migration from FinFET to NsFET, to enable further gains in current drive while reducing the device surface, thus enabling smaller, faster and more energy-efficient chips (Figure 3). The three different categories of applications should remain: high performance computing (severs, data centers), general purpose (laptops, gaming), and low power (mobile, IoT) with significant differences in terms of acceptable leakage current (IOFF).Moving to Nano Sheet FETs varies depending on the foundries. This situation is somehow similar to the transition from MOSFET to FinFET initiated by Intel in 2011. Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s FinFET transistors to GAA FETs at the 3nm and 2nm nodes, starting either next year or in 2023. GAA FETs hold the promise of better performance, lower power and lower leakage. Samsung plans to introduce the world’s first nanosheets at 3nm in the 2022-2023 time frame. TSMC is developing 2nm GAA for initial launch in 2024 or 2025.The technology will require entirely new fabs. With the cost of these new fabs in the $20 billion range, this isn't something the industry is approaching without careful consideration.

Video Lecture on this topic is here :

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