Scaling degrades perfomance of deep submicron MOSFET devices. Vd controls the channel and Vg losses control over channel. Vg is unable to shut off the channel completely in the off-mode of operation, which leads to an increased Ioff between drain and Source. Multiple-gate field-effect transistors (MGFETs), emerged as an alternative to planar MOSFETs. MGFETs demonstrate better control over channel and MOSFET performance. Among all MGFETs, FinFETs (a type of DGFET) and Trigate FETs (another popular MGFET with three gates) have emerged as the most desirable alternatives to MOSFETs due to their simple structures and ease of fabrication.
Leakage Current and Novel Structures:
Gate cannot control leakage path far away from gate. SOI MOS structure reduce leakage and chance of latch up. Addition of another gate can increase control over channel. The main idea of a DG MOSFET is to control the Si channel more efficiently compared to planar MOSFET. Si channel width is usually kept small and voltage is applied on both sides of channel. Such a structure and operation effectively suppress short channel effects and leads to higher currents as compared with a MOSFET having only one gate.
Evolution of Different Multi Gate FET:
What is FinFET?
A multigate non-planar Field Effect Transistor. Channel is wrapped with gate from two/three sides. FinFET is Fin-Shaped-FET. Fin is a body part of fish which stick out of its body. A Silicon Fin forms its body. The channel of the FinFET is vertical.
Lg = gate length , Tsi = fin thickness , Hfin = fin height
Can be built over bulk silicon or SOI wafer.
For double-gate: W = 2 ∙ Hfin ; For tri-gate: W = 2 ∙ Hfin + T
Different Types of FinFET:
Two types of Gate design :
i. Double Gate FinFET
ii. Triple Gate FinFET
Two types of gate connection :
i. Shorted Gate FinFET (SGFinFET) : 3 terminal device.
Front and back gate are physically connected/shorted. Electrostatics of channel is controlled by both gates together.
ii. Independent Gate FinFET (IGFinFET) : 4 terminal device.
Gates are isolated. Different voltages can be applied to gates. This flexibility is very useful.
Two types of Wafer :
i. Bulk FinFET
ii. SOI FinFET
Planar MOSFET vs FinFET :
FDSOI MOSFET vs FinFET
Bulk FinFET vs SOI FinFET
Corner Effect:
Corner Effect :
Charge accumulation at corners or areas with higher curvature are higher (basic Physics). So electric field at corners are higher. Same rule follows for FinFET. Charge accumulation and electric field higher at corners. High channel doping create premature inversion at the corners due to charge accumulation. Electric field coupling in device corners results in lower threshold voltage of corner regions. Corners are turned on earlier (at lower gate voltages) than the other parts of the channel. This doesn’t exist in the other parts of thesilicon/silicon-dioxide interface. This means that different regions of the transistor with high electron density are activated at different gate voltages. This premature inversion at the corners of the triple gate FinFET degrades the sub-threshold characteristics of the FinFET which results in higher off state leakage. The corner effects must be suppressed to avoid leakage currents. There are various techniques available toeliminate the corner effects, such as, reduction in doping concentration in channel, and corner rounding etc.
Process Variations :
FinFETs suffer from process variations. Due to small dimensions and lithographic limitations, FinFETs are subjected to physical fluctuations, like variatioins in gate length , fin- thickness , gate-oxide thickness and gate underlap . Gate oxide is on the etched sidewall of the fin, and may suffer from nonuniformity. The degree of nonuniformity depends on the line-edge roughness (LER) of the fin.
FinFET Fabrication Flow – 1 & 2
Wafer Preparation:
Cleaning of wafer. Base is a lightly p-doped substrate with a SiN (silicon nitride) hard mask and a patterned resist layer on top .
Fin etching :
Highly anisotropic etch process is used. The etch process is time based as there is no stop layer on a bulk wafer. In 22 nm process the width of the fins might be 10 to 15 nm, whereas the height would must be twice of that or more.
Oxide deposition :
To isolate the fins from each other a oxide deposition is
done.
Planarisation :
Planarisation is done. This is the process to increase the
smoothness or planarity of a wafer through process like CMP.
Recess etch :
Another etch process is needed to recess the oxide film to form a lateral isolation of the fins.
Gate oxide :
Gate oxide is deposited on top of the fins by thermal oxidation to isolate the channel from the gate elctrode. Since the fins
are still connected underneath the oxide, a high- dose angled implant at the base of the fin creates a dopant junction and
completes the isolation (not illstrated).
Gate Formation :
A highly n+ doped poly silicon layer is deposited on top of the fins, thus up to three gates are wrapped around the channel:
one on each side of the fin, and - depending on the thickness of the gate oxide on top - a third gate above.
Since there is an oxide layer on an SOI wafer, the channels are isolated from each other anyway. In addition the etch process of the fins is simplified as the process can be stopped on the oxide easily.
FinFET Advantages:
Better control over the channel
Suppressed short-channel effects
Lower static leakage current
Faster switching speed
Higher drain current (More drive-current per footprint)
Lower switching voltage
Low power consumption
FinFET Disadvantages:
Self-Heating Effect
Quantized device-width. It is impossible to make fractions of the fins, whereby designers can only specify the devices’ dimensions in multiples of whole fins.
In this insightful article, we delve into several key aspects within the realm of VLSI technology, focusing primarily on the groundbreaking concept of Strained Silicon as a channel material. Our discussion encapsulates the significance of Strained Silicon, positioning it as a pivotal milestone in the evolution of VLSI. Throughout the video, we unravel the intricate details surrounding Strained Silicon, exploring fundamental questions such as the nature of SiGe (Silicon Germanium) and the application of strain in Silicon. The discourse extends to a comprehensive examination of the band structure of Silicon, shedding light on the nuanced effects of biaxial tensile strain and compressive strain. By addressing these critical facets, we aim to provide a thorough and elucidating overview of the multifaceted world of VLSI technology and its transformative Strained Silicon component.
VLSI Milestone & Strained -Si:
From 90 nm technologies, the performance boost by method of MOSFET dimension scaling started to diminish. MOSFET scaling resulted in several physical limitations. Higher body doping leads to lower carrier mobility, higher junction capacitance, increased junction leakage Thinner gate dielectric leads to higher gate leakage Strained Silicon channel has been introduced as technology booster. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels and drive current, respectively, at the same supply voltage and gate oxide thickness. Tensile and compressive strain applied to channel. Strain changes lattice constant and energy band structure of silicon.
What is Strain Si?
Strained Silicon is literally Silicon which is strained. Strain is induced using different mechanism. In Strained-Si atoms are stretched beyond their normal inter-atomic istance. Advantage of s-Si relies in its ability to fundamentally alter the band structure in ways that increase the effective mobility. The basic idea in strained Si CMOS is to modify the carrier transport properties of Si by introducing strain in order to improve performance of MOSFETs. Mobility improvement in strained silicon takes place mainly due to the reduction of the carrier conductivity effective mass and the reduction in the inter-valley phonon scattering rates. Semiconductor with smaller lattice constant than substrate leads to compressive stain on top layer. Semiconductor with larger lattice constant than substrate leads to tensile strain on top layer.
What is SiGe?
SiGe is an alloy with any molar ratio of silicon and germanium, i.e. with a molecular formula of the form Si1−xGex. Used as a semiconductor material in integrated circuits (ICs) as a strain-inducing layer for CMOS transistors. The biaxial tensile strain in the strained Si layer on relaxed SiGe can be tailored by the Ge content.
How strain is applied in Si?
Two types of strain : Tensile and Compressive strain. Two direction of strain : Biaxial and Uniaxial Strain.
Biaxial strain/Global Strain :
Introduced by epitaxial growth of Si and SiGe layers. The strain is induced by the lattice mismatch between Si and SiGe.
Advantages : Uniformly strained layers obtained. Can be implemented with standard CMOS process with minimal modification.
Disadvantages :Limited improvement of PMOS transistor performances, occurrence of defects and dislocations at the boundary surfaces, increased production costs.
Uniaxial /Local Strain :
Introduction of local structures and materials cause strain in the channel of transistors. This is local/uniaxial strain.
In pMOS the source and drain are formed by epitaxial SiGe which introduce uniaxial compression in the channel area . A tensile capping layer in nMOS creates uniaxial strain.
Band Structure of Silicon:
Each energy level of silicon is composed of six equal energy valleys in three dimensions. In inversion layers, these six valleys are split into two fold out of plane valleys located at the kz axes (001) direction and four fold in-plane valleys in kx (010) direction and ky axes (100) direction. The electrons in all these conduction valleys have transverse mass (mt =0.19m 0 ) and longitudinal mass (m l = 0.916m 0 ). Clearly ml > mt .
In the two fold valleys, the electrons have transverse mass parallel to the MOSFET Si/SiO2 interface and longitudinal mass perpendicular to the interface.
On the other hand, in four fold valleys, the electrons have transverse mass perpendicular to the MOSFET Si/SiO 2 interface and longitudinal mass parallel to the interface. There are three valence band subband : HH,LH and SO.
Impact of Biaxial Tensile Strain :
With tensile strain, two out of plane (∆ 2 )valley move lower and the ∆ 4 valleys move upward energitically. This band alteration gives an alternate lower site for electrons to reside i.e. ∆ 2 valleys. Value of mt in the lower energy valleys ∆ 2 is lesser than the ∆ 4 valleys in the direction parallel to the interface suitable for the flow of electrons from the source to drain. Inter-valley phonon scattering between the lower and upper states is decresed. Due to this, the electron mobility increases. With strain, valence sub-bands splits and their shapes changes. HH and LH bands split and move away and SO hole subband move downward further. Both in-plane and out-of-plane hole mobility is improved mainly due to the reduced inter-band and intra-band scatterings.
Impact of Compressive Strain:
Both biaxial and Uniaxial stresses have similar effect on the conduction band structure whereas the effects on the valance band are much different. Hence, the mobility gain is similar for uniaxial and biaxial strain, as it results from the splitting of the six-fold degenerate conduction band valleys for both types of stress.
The uniaxial strain has much more significant advantageous effect on the valance band relative to biaxial stress.
In this extensive article, we thoroughly explore various essential aspects related to VLSI technology and SOI MOSFET. The discussion commences with an introduction, providing viewers with an initial overview, followed by a helpful chapter index for easy navigation through subsequent topics. The focus then shifts to VLSI milestones and the significance of SOI MOSFET. A detailed exploration of SOI follows, including an explanation of what SOI is and an in-depth examination of its fabrication process in three parts. The video proceeds to unravel the reasons behind VLSI's adoption of SOI, contrasting it with the drawbacks of Bulk MOSFET. Further insights into the advantages of SOI are provided, followed by an intricate analysis of the performance of SOI MOSFET. Specific attention is given to the phenomena of Kink Effect and strategies for reducing Floating Body Effect. The video concludes with a comparative exploration of FDSOI vs PDSOI, offering viewers a comprehensive understanding of the intricate aspects of SOI MOSFET technology in the field of VLSI.
VLSI Milestone & SOI MOSFET
Moore's law has been the main driving force for last few decades. Device dimension reduced and performance got boost. Down scaling has resulted in short channel effect. New device structure like SOI has been introduced. Global Foundry has developed SOI solutions for high-growth, high-volume wireless and WiFi markets. FD-SOI is a suitable technology for new standards for IoT, automotive and mobile connectivity applications.
What is SOI?
SOI or Silicon-on-Insulator refers to a technology where MOS device is fabricated on silicon-insulator-silicon substrate rather than conventional silicon. SOI MOSFET is fabricated as three layered device,the bottom most layer is the substrate which is lightly doped. The uniform buried layer of silicon dioxide which is called as buried oxide layer (BOX), supporting substrate or handle wafer or base wafer. The SOI is also a 4 terminal device source, drain, gate and the body. In SOI based devices Silicon junction and channel area are above electrical insulator like SiO2. Choice of insulator depends on application. Sapphire is used for high performance radio frequency (RF) and radiation sensitive application. SiO2 is used for microelectronics applications to minimise short channel effect. The width of the silicon film decides whether the SOI is fully depleted or partially depleted. If the width of SOI film laid over the buried oxide is thin, the device is said to be fully depleted or FDSOI. If the width of the SOI film is thick, it is said to be partially depleted or PDSOI. The thickness of the SOI layer for an FD-SOI MOSFET is usually about one-third the effective channel length in order to avoid a punch-through current. Thickness of BOX varies depending on application.
SOI Fabrication Process :
There are few unique ways to fabricate SOI Wafers, such as : SOS (Silicon On Sapphire ), Bonded and Etch back SOI, SIMOX (Separation By Implanted Oxygen), ELTRAN (Epitaxial Layer TRANsfer) , Smart-Cut .
i. Silicon on Sapphire (SOS) :
SOS wafers are formed by depositing Si onto the sapphire substrate at very high temperatures. Very pure sapphire crystal is grown in a controlled lab environment and the Si can be cleanly deposited on the surface of the sapphire wafer.
ii. Bonded and Etch back SOI (BESOI) :
Thermally oxidize the wafer. Another wafer is bonded over the previous one by method os SFB or Silicon Fusion Bonding. Silicon fusion bonding (SFB) is the joining together of two silicon wafers without the use of intermediate adhesives. Now the bonded wafer is etched to get the required thickness of SOI.
iii. SIMOX Method :
iv. SmartCut Fabrication Process :
v. ELTRAN (Epitaxial Layer TRANsfer):
Why VLSI Adopted SOI?
i. DIBL :
For a long-channel device a drain bias can change the effective channel length although the source barrier remain same. For a short channel device , the drain is closer to the source as compared to long channel device. So, drain bias can influence the barrier height at the source end. Figure shows the energy bands along the semiconductor surface. For a short-channel device, this lowered barrier with decreasing channel length or increasing drain bias is commonly called drain-induced barrier lowering (DIBL).
ii. Punch Through :
It a break down mechanism. Occurs when the sum of depletion layer width for source and drain junctions is comparable to the channel length. The depletion region of the drain and source junctions gradually merge together as the drain voltage is increased, causing current to flow irrespective of Vg at high Vd.
iii. CMOS-Latch Up :
Parasitic BJTs in a CMOS structure forms feedback loop and create a PNPN structure. Such latched up condition create low impedance path between Vdd and Vss. High current flows and the IC gets damaged.
iv. Junction Capacitance :
Cj = Junction Cap. Cd= Depletion Cap.
Cg = Gate Cap. Cov =Overlap Cap.
v. Leakage Current :
Gate Current Tunneling , Hot Carrier Injection
Subthrehold Current, Reverse Bias Jn. Current,
Gate Induced Drain Leakage, Channel Punch Through Current
Advantages of SOI :
SOI MOSFETs have a bunch of advantages compared to to trheir Bulk Silicon counterpart. Such as :
1. Reduction in : 1. Drain /source parasitic capacitances, 2. Delay,dynamic power consumption, 3. Leakage current.
2. Due to an oxide layer, the threshold voltage is less dependent on back gate bias compared to bulk CMOS. This makes the SOI device more suitable for low power applications.
3. SOI devices have no latch-up problems as there is no substrate to form PNPN structure.
5. SOI devices have excellent radiation hardness to alpha particles, neutrons, and other particles. Alpha particles are generated by small amounts of radioactive elements in IC materials.
6. SOI allows more devices per die area due to absence of wells and the possibility of direct contact of the source-drain diodes in the NMOS and PMOS transistors.
7. BOX coupled with ground plane (GP) suppress fringing electric fields through the BOX and substrate. So front-gate-to-channel control increases and DIBL lowers.
8. Faster device operation (speed/power product) due to reduction of parasitic capacitance (primarily due to reduced source-drain junction capacitance, but also from gate-to-substrate capacitance and metal-to- substrate capacitance).
9. Performance improvement happens equivalent to next technology node without scaling (e.g., performance of 0.25 micron devices on SOI wafers equivalent to performance of 0.18 micron devices on bulk wafers) .
10. Potential to simplify device fabrication steps. Fewer masks and ion implantation steps, made possible by the elimination of well and field isolation implants. Less complex (costly) lithography and etching required to achieve next-generation performance.
Performance of SOI MOSFET :
i. Threshold Voltage :
A thick-film SOI device, behaves like a bulk device due to absence of interaction between the front and back depletion regions, the threshold voltage is same as in a bulk device. For a thin- film SOI device, the threshold voltage is a function of the different possible steady-state charge conditions at the back interface.
ii. Body Effect :
In an SOI transistor, the body effect is defined as the dependence of the threshold voltage on the back-gate bias. In a thick film device, the body effecty (i.e. back-gate effect) is negligible due to absence of coupling between the front and back gate.
iii. Floating Body Effect : Floating body effect (FBE) is the major parasitic effect in SOI-MOSFETs and is a consequence of the complete isolation of the transistor from the substrate. The effect is related to the built-up of a positive charge in the Si body of the transistor, originating from the holes created by impact ionization. This charge cannot be removed rapidly enough, primarily because no contact with the Si film (body) is available. Self heating, bipolar currents and kink effect are said to be the major disadvantages of SOI technology when the body is left floating.
iv. Floating Body and Parasitic Bipolar Effects:
The presence of a floating volume of silicon under the gate is the origin of several effects, generically referred to as floating body effects. There exists a parasitic bipolar transistor in the MOS structure. If we consider an n-channel device, the N+ source, the P-type body and the N+ drain indeed form the emitter, the base, and the collector of an NPN bipolar transistor, respectively. In a bulk device, the base of the bipolar transistor is usually grounded by means of a substrate contact. But, due to the floating body in an SOI transistor, the base of the bipolar transistors is electrically floating. This parasitic bipolar transistor is origin of several undesirable effects in SOI devices.
v. Self Heating Effects:
Due to thermal isolation of substrate by the buried insulator in an SOI transistor, removal of excess heat generated by the Joule effect become critical. It leads to substantial elevation of device temperature. The excess heat mainly diffuses vertically through the buried oxide and laterally through the silicon island into the contacts and metallization. Due to the relatively low thermal conductivity of the buried oxide, the device heats up to 50 to 150C. This increase in device temperature leads to a reduction in mobility and current drive, thus degrading the device performance over a period of time.
vi. Kink Effect :
The kink effect is appearance of a kink in the output characteristics of an SOI MOSFET under strong inversion. The kink is very strong in n channel transistors, although absent from p-channel devices. In a thick-film or n-channel PD SOIMOSFET. When Vd is high enough, the channel electrons can acquire sufficient energy in the high electric field zone near the drain to create e-h pairs, due to an impact ionization mechanism. The generated electrons move into the channel and the drain, whereas the holes, which are majority carriers in the p-type body, migrate towards the place of lowest potential i.e., the floating body. The injection of holes into the floating body forward biases the source-body diode.The increase of body potential gives rise to lowering of threshold voltage and source-body potential barrier. More minority carriers are able to flow from source to the channel, thereby causing an excess drain current and producing many more pairs through the avalanche process. This positive feedback results in a sudden increase in Id or kink in output characteristics.
More on Kink Effect
FDSOI MOSFET and Kink Effect :
The electric field near the drain is lower in the FDSOI than in PDSOI. As a result, less electron-hole pair generation takes place in the fully depleted device. Also, in FDSOI, the source-to-body diode is already forward biased due to the full depletion of the film, and therefore, holes can readily combine in the source without having to raise the body potential there. That is why FDSOI is free of kink effect.
P-Channel SOI-MOSFET and Kink Effect :
The p-channel devices are free of kink effect because coefficient of electron-hole pair generation by energetic holes is much lower than that by energetic electrons. The kink effect is not observed in bulk devices as the majority carriers generated by impact ionization can escape into the substrate or to a well contact. The kink effect can be eliminated from the partially depleted SOI MOSFETs if a body contact is provided for removal of excess majority carriers from the device body.
Reducing Floating Body Effect
Body Contact :
Contacting silicon underneath the gate region to the ground effectively suppresses the kink effect as well as the parasitic lateral bipolar effects. Several schemes exist to provide the transistor with body contact. It consists of a P+ region which is in contact with the P-type silicon underneath the gate.
Source Body Tie Structure:
A more compact method, source body tie structure. P+ body ties are created on the side of the N+ source diffusion. If the device width is large, additional P+ regions can be formed in the source (such that a P+ N+ P+ N+ structure is introduced). Such a device has the main drawbacks of being asymmetrical (source and drain cannot be switched), and the effective channel width is smaller than the width of the active area.
FDSOI vs. PD SOI:
FDSOI devices are naturally free from kink effect .FD SOI has an enhanced sub-threshold swing, S . Therefore FD devices operate faster because of a sharper sub- threshold slope, and a reduced threshold voltage that allows for faster switching of the MOS transistors. These transistors also have increased drive currents at relatively low voltages. Fully-depleted SOI devices have the highest gains in circuit speed, reduced power requirements and highest level of soft-error immunity. Interface coupling effect affects operations of FDSOI. their operation. The interface coupling is inherent to fully depleted SOI devices, where all parameters (threshold voltage, trans-conductance, interface-trap response etc.) of one channel are insidiously affected by the opposite gate voltage (at the buried oxide). The threshold voltage fluctuation due to SOI thickness variation is one of the most serious problems in FD SOI MOSFETs. PDSOI devices are built on a thicker silicon layer and are simpler to manufacture. Most design features for developing PD devices can be imported from the bulk silicon devices and used in the SOI environment with only modest changes. This makes circuit redesign for the PD devices simpler than for the FD microcircuits.
