Reliability issues and IC failure in VLSI

Developing IC is a time, labor,research and money extensive process. There are some physical and electrical reasons, which  can spoil the whole effort we put into. Therefore we must understand and analyse what reasons can fail this development process. In this article we will discuss about reliability issues in CMOS and try to understand reasons that leads to IC failure. This informative article meticulously examines various pivotal aspects surrounding the reliability of VLSI CMOS technology.

 

What is Reliability?

Reliability means how likely it is that a product/system/service will work well for a certain amount of time or under specific conditions without any issues.

In simpler terms, reliability is like:

i. Probability of success , 

ii. Durability , 

iii. Dependability

iv. Quality over time , 

v. Availability to do its job

Failure is deviation from compliance with the system specification for a given period of time. Failures can happen for different types of faults. Reasons might be design bugs, manufacturing defects, wear out of oxide or interconnect, external disturbances or intentional manhandling of a product. Although not all faults lead to errors.  A number of physical failure mechanisms that can affect the reliability of a CMOS ASIC. 

Yield and Reliability are two of the most important aspects for the development of new technology. Designing a reliable CMOS chips involves understanding and addressing of the potential reasons of failure.

Reliability Factors – I & II

If a device is used under the wrong use conditions, a failure may occur. Reliability of a device depends on how much stress it can handle. Some factors related to failure are :

i. Electric load, ii. Temperature, iii. Humidity, iv. Mechanical Stress, v. Static Electricity, vi. Effect of Repeated Stress

(i) Electric Load :

- Operation conditions determines the life of semiconductor devices.

- Electric power cause a rise of the junction temperature which might lead to device failure. The electric current should be lowered as far as possible.

- It is necessary to handle the surge current that flows when the switch is turned on or off and the surge voltage of inductive (L) load so that they do not exceed the maximum rated values.

(ii) Temperature :

-Temperature affects the life of semiconductor products. A rapid or gradual change results in deterioration of characteristics leading to device malfunction.

- The relation between the life “L” and temperature “T” :

- The life will be shortened if temperature rises.

- A ventilation device or heat radiation device used to avoid overheating issue.

(iii) Humidity:

- Usually IC chips are covered with surface protective film to protect from humidity. If a device is operated under severe humidity conditions, it should be operated particularly carefully.

(iv) Mechanical Stress :

- If the device is strongly vibrated during transportation, or if an extremely strong force is applied to a device during installation, the device may be directly, mechanically damaged. In addition, moisture or a contaminant may enter the device through the damaged area, and may cause deterioration of the device.

(v)  Static electricity:

- Electrostatic charge damages the equipment. Equipment incorporating devices is often charged with static electricity. In some cases, an Recently, plastic is generally used for the casing and the structure of equipment.

- Human bodies can be also charged with static electricity.

- While handling semiconductor devices, it is necessary to take static charge preventive measures

- This issues became more serious as device dimensions are aggressively scaled and operating frequencies becoming higher.

(v)  Effect of repeated stress :

- If a stress is repeatedly applied it might be stronger than steady stress.

- A high-low temperature cycle and intermittent internal heat generation cycle can apply stresses repeatedly. The effects of such cycles, such as rearrangement of the material structure and fatigue deterioration of resistance to distortion,are examined and utilized for evaluation of failures.

Failure Mechanisms  

(a) Time Dependent Dielectric Breakdown (TDDB):

Gate oxide thickness has reduced with technology nodes. Electric field across Tox is getting ever stronger. Oxide film breakage is caused by : (i) an initial defect , (ii) deterioration of the oxide film. Initial defect leads to an early failure. Deterioration of the oxide film leads to long-term reliability failure. Oxide layer breaks down if applied electric field exceeds dielectric breakdown withstand voltage. Even if electric field with lower value is applied for linger period of time may also cause breakage as time elapses. This type of breakage is referred to as a time dependent dielectric breakdown (TDDB). An empirical formula expresses the TDDB life :

t: Life in practical use (h) ; 

tt: Life in test (h) ; β: Electric field acceleration factor; 

E: Electric field strength in practical use (MV/cm)

Et: Electric field strength in test (MV/cm); Ea: Activation energy (eV) ;

k: Boltzmann constant (eV/K) ; 

T: Temperature for actual use (K) ;

Tt: Test temperature (K)

Effective methods to prevent these failures are:

(i) optimising the process in order to minimise variability.

(ii)formation an oxide film with less defects,

(iii) screening by use of high electric field during inspection/burn-in.

(b)Negative Bias Temperature Instability (NBTI) :

Four types of electric charge exist in gate oxide films:

(1) Mobile ionic charge Qm , (2) Fixed oxide charge,

(3) Interface trapped charge Qit , (4) Oxide trapped charge Qot

NBTI is an increase in the absolute threshold voltage, a degradation of the mobility, drain current and transconductance of p – MOSFETs at either negative Vg or elevated temperatures.  A stronger and faster NBTI effect is produced by their combined action.  Such fields and temperatures are typically encountered during burn in and during routine operation in high-performance ICs.

Si has 4 valence electrons ==>  At the surface of the silicon crystal atoms are missing and traps are formed. The density of these interface states Dit. After oxidation most interface states are saturated with oxygen atoms, interface quality improves. To reduce the number of dangling valence bonds further, surface is annealed with forming gas (mixture of Hydrogen and Nitrogen). The dangling silicon bonds are passivated by forming Si-H bonds. The number of electrically active interface states can be reduced to acceptable range.

These Si-H bonds have lower binding energy. Elevated temperature and high electric fields break these bonds and interface states reactivated. The exact properties of the interface defects, which are trivalent silicon atoms with one unpaired valence electron depends on the exact atomic configuration and on the orientation of the substrate. Holes interact with Si-H bond and weaken Si-H bond  At elevated temperature, the Si-H bonds dissociate : Si 3 ≡ SiH + h + → Si 3 ≡ Si • + H +

The effect of bias temperature instability can be observed in both, p-channel and n-channel MOSFETs. However p-channel MOSFETs with negative Vg stress are more susceptible to this kind of degradation. It has been reported that for NBTI degradation, channel cold holes are important. As the n-channel MOSFET biased into accumulation also has holes at the surface of the substrate, the threshold voltage shift should be similar to p-channel MOSFETs. Therefore, the lack of holes can not be the cause for the different degradation behavior.

Impact of NBTI on Circuits :

(i) Occurs primarily in p-channel MOSFETs with negative gate voltage bias and is negligible for positive gate voltage.

(ii) Usually occur during the “high” state of p-MOSFETs inverter operation.

(iii) Leads to timing shifts and potential circuit failure due to increased spreads in signal arrival in logic circuits.

(iv) Asymmetric degradation in timing paths can lead to non-functionality of sensitive logic circuits product field failures.

(c)Hot Carrier Injection (HCI):

Hot carrier injection is one of the most significant problems regarding reliability of state-of-art MOSFET. It is difficult to reduce the power supply voltage. For DSM and nano devices electric field strength is increasing. Hot carrier is a generic name for high-energy hot electrons and holes generated in the transistor. Hot carriers injection into a gate oxide film generate the interface state and fixed charge, and finally deteriorate the Vt and Gm of the MOSFET. As the Vt of the FET is increased, the circuit operation will become slow, and will finally operate abnormally. Hot Carrier is easily generated when the Vg < Vd/2 . When Vd> Vg, the carriers present in the channel will impact the Si crystal lattice and generate pairs of a hot electron and a hot hole (Impact Ionization). These pairs function as hot carriers. Hot carriers under strong Vd gain enough energy to break the barrier of Si/SiO2 inrterface and go through the gate oxide into the gate. As a result, either the gate oxide film is charged, or Si/SiO2 interface is damaged.

This lead to change is transistor characteristic. Generation mechanism : Channel hot electrons (CHE), Avalanche hot carriers (AHC), Substrate hot electrons (SHE). 

AHC shows remarkable change when devices are miniaturized.

(d) Soft Error : 

A very small amount of radioactive elements (U, Th etc.) are present in the package material. Abnormal operation of devices is caused by α particles radiated from that radioactive element. This problem is referred to as a soft error. This abnormal operation is temporary. So writing data again can restart normal operation. This problem is more dominant in advance node devices. In this dimension , the electric charge of signals handled in the devices is lowered. The electric charge of the noise generated by α particles that are radiated in the chip has a large impact that cannot be ignored.  The α particles are generated at the cell capacitor that stores 1-bit data (1 bit = minimum data unit of dynamic RAM).  The α particles generates electron-hole pairs in the substrate. The α particles loose their energies in generating the e-h pairs. The electrons generated in this process can invert the data of the cell capacitor. A cell capacitor is considered “L” if electrons exist and considered “H” if electron do not exist. If electrons are generated in the cell capacitor by α particles, data “H”will be inverted to data “L”. This is referred to as a soft error in the memory cell mode. Soft errors affect memories, registers, and combinational logic. Memories use error detecting and correcting codes to tolerate soft errors, so these errors rarely turn into failures in a well-designed system.

The cell capacitor data is read out to the bit line by diffusion, and then compared with the reference potential. If electrons generated by α particles flow into the bit line, the potential of the read out data or the reference potential may be lowered. If the data potential is lowered, data will be inverted from “H” to “L”. If the reference potential is lowered, the data will be inverted from “L” to “H”. This is referred to as a soft error in the bit line mode.  If the operation cycle (cycle time) of the dynamic RAM is shortened, the reference potential will be compared with the data potential more frequently. As a result, soft errors in the bit line mode will be increased. On the  other hand, change in the cycle time will not affect the soft errors in the memory cell mode. 

 Prevention of Soft Error :

(i) to use package material that contains less radioactive elements (α particle generative source).

(ii) to prevent α particles from entering the chip by coating organic material on the chip.

(iii) improvement of the bit line structure using wire materials of Al, poly-Si, etc., improvement of the sense amplifier, adoption of the return bit line etc.

(e) Electromigration (EM)

A chip may go above 100 Degree Celsius during practical operation. High frequency power loss & consequent heat dissipation contributes in increased temperature. Rise in temperature enhances solid-state metal ion diffusion. Electromigration is caused by scattering of the moving electrons with the ions, i.e., by momentum transfer between electrons and ions in metal interconnects. This ion-electron interaction is sometimes referred to as "electron wind.” This causes the wire to break or to short circuit to another wire.   Such situation void in interconnects can leads to open circuit i.e chip failure.

EM is one of the most menacing and persistent threat to interconnect reliability. Mean time to failure due to electromigration:

MTTF : Mean time to failure (h) , A : Constant of wire, J : Current density (A/cm2), n : Constant ,  Ea : Activation energy (eV) , k : Boltzmann constant (eV/K), T : Absolute temperature of wire (K)

The following factors can reduce the failures caused by electromigration:

a) Crystal structure (grain diameter, crystal orientation, etc.)

b) Addition of other elements to metal film

c) Laminated wiring structure

Electromigration depends on the current density J = I/wt. It is more likely to occur for wires carrying a DC current where the electron wind blows in a constant direction than for those with bidirectional currents.

(f) Self Heating:

Bidirectional wires are less prone to EM.  Although their current density contributes in by self-heating. High currents dissipate power in the wire. Since surrounding oxide or low-k dielectric is a thermal insulator, the wire temperature can become significantly greater than the underlying substrate. Hot wires exhibit greater resistance and delay.  EM is also highly sensitive to temperature, so self-heating may cause temperature-induced electromigration problems in the bidirectional wires. Brief pulses of high peak currents may even melt the interconnect. A significant percentage of the device self-heat energy flows vertically and laterally to interconnect layer. The local temperature rise depends upon the thermal dissipation path(s) away from the heat energy originating element. Self-heating is dependent on the RMS current density. A conservative rule to control reliability problems with self-heating is to keep Jrms < 15 mA/Rm2 for bidirectional aluminum wires on a silicon substrate.

The maximum capacitance of the wire can be estimated based on the RMS current. EM from high DC current densities is primarily a problem in power  and ground lines. Self-heating limits the RMS current density in bidirectional signal lines.

(g) Stress Migration :

Stress migration/stress-induced voiding (SIV) is wear out failure mechanisms in chip metallization. It causes an open circuit in the metal interconnects, especially at the via, since it is the weakest link. SM is caused by the interaction between the thermo-mechanical stress in the interconnect system and the diffusion of vacancies. The existence of thermal stress in the interconnect is caused by thermal expansion mismatch between the metal and the surrounding materials. The BEOL interconnect structure consists of several different materials like metal, dielectric, diffusion barrier, silicon substrate and capping layer. Fabrication of the structure involves several  thermal cycles from room temperature to about 400°C, a large amount of stress can be introduced due to the thermal expansion mismatch among these materials. Metal expands due to heating and then contracts during the cooling process although unable to retract to the original, since the metal is constrained by other material. As result, there is a tensile stress in metal layer. Metal atoms moves to balance stress condition, thus void is created. Void in metallization tends to nucleate and grow around the vias and blocks the flow of electrical current due to open ckt condition.

(h)CMOS Latchup :

A latch-up is a destructive short circuit phenomenon to the CMOS Structure. It can be defined as a low resistance path between voltage levels. It is caused by low-impedance path between the power supply rails of a MOSFET circuit through PNPN parasitic structure underneath. The circuit function is disrupted by latchup and currents are frequently large enough to cause permanent damage. The parasitic PNPN structure resembles and equivalent to Silicon Controlled Rectifier (SCR) structure. A PNPN structure which created by a PNP and an NPN transistor stacked next to each other. 

Immediately after latch up trigger, one of the transistors starts conducting and the other one begins follows it by start conducting.  They both stay in saturation for as long as the structure is forward-biased and some current flows through it.

(i) Electrostatic Discharge:

ESD is the release of stored static electricity. The most famous ESD (large scale) is lightning. ESD event that take place in chip is not visible.  ESD destroys about 20 % of electronic components before they are installed into a  system. ESD may only damage a component but it leads to further subsequent damages within a brief time during circuit operation. A person can acquire charges by simply walking across a room. When such a charged person/object then approaches an IC, an ESD event occurs, characterized by a high current within a few ns. A high current density and/or electric filed can damage conductor, semiconductor and insulator in an IC. Electrostatic straps are used in industry to protect from ESD where electronics circuits are packaged and assembeled. The circuit present inside the IC, will tend to be partially damaged or might breakdown when this high voltage pulse enters. When we buy different semiconductor component for computers we get it in a dark grey package , that is a external protection for ESD event. ESD in an IC is usually start with the oxide breakdown which result in percussion path. The high current density damages the semiconductor devices through thin-film fusing, filamentation, and junction spiking. The high electric field, on the other hand,can cause failure through dielectric breakdown or charge injection.

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Variability issues in VLSI

Manufacturing CMOS circuit is a huge task. A small variation in process parameter can impact device performance. and introduce variability. In this article we have discussed how variability art different stage of CMOS manufacturing impact the final performance, how variability leads to PVT corners and how we model them.

In this article , comprehensive exploration was undertaken, delving into various aspects surrounding the construction of CMOS technology. The discussion touched upon the intricate challenges inherent in CMOS development, emphasizing the significance of addressing variability and the diverse levels of abstraction involved in the process. Notably, the discourse delved into the critical factors contributing to process variation, including voltage (V) and temperature (T) fluctuations, and the essential concept of design corners. Furthermore, the presentation meticulously elucidated the sources of process variations, categorizing them into distinct segments for thorough examination. The subsequent segments of the discussion meticulously examined the impacts of process variations on crucial parameters such as carrier mobility, Cox, Vth, W, L, yield, delay, and energy consumption, shedding light on the multifaceted ramifications across these domains. Moreover, the discourse also delved into the analysis methodologies essential for comprehensively studying variability, as well as the crucial aspect of modeling variability for accurate prediction and optimization within CMOS technology.

Challenges to build CMOS: 

It is challenging to fabricate millions /billions of transistors which will work flawlessly for 10^18 cycles.  Transferring exact shape to Silicon wafer or creating uniform doping profile are challenging.  Operating condition might range from freezing to boiling.  Intense electric fields gradually break down the gates. Continuous flow of current carry away the atoms of the wires.Cosmic rays zap the bits stored in tiny memory cells. Manufacturing/environmental  variations has impact on chip. Design must include impact of manufacturing variations and changing operating conditions.  

There are three different sources of variation :

a. Process Variation [P]

b. Supply Voltage [V]

c. Operating Temperature [T]

Aim is to design a circuit that operate reliably over all extremes of P, V and T. Causes poor yield and circuit performance.

Variability and Level of Abstraction:

Fabrication process steps such as oxidation, ion implantation, lithography, chemical-mechanical planarization (CMP) introduce variability in device. Random variations in operating conditions such as the temperature and the power supply voltage (Vdd ) increases with circuit clock frequency leading to circuit performance variations. This degrades yield and increase production costs. Variation of performance metric of a circuit like delay, dynamic power and static power consumptions ultimately propagate their negative influence on the overall performance of a Chip.

Process Variation (P):

Process Variations classified as :

1. Lot-to-lot (L2L) [Lot is batches of wafer ]

2. Wafer-to-wafer (W2W )

3. Die-to-die (D2D), inter-die, or within-wafer (WIW )

4. Within-die (WID) or intra-die

Variability in lot-to-lot, wafer-to-wafer and chip-to-chip are almost equally applied to every transistor on the chip. These Inter-Die variations,are called “global variations”. The remaining within-chip or Intra-Die variations referred as “local variations.” Global and local variations must be modeled accurately. That helps in estimating the power and performance scaling with circuit complexity. Local variations get averaged out for large number of transistors or long critical paths.  Global variations usually add up and shift the average power/performance of the entire chip.  D2D variations make one chip faster/slower than another. WID variations become important in nano-meter processes.

Voltage (V) & Temperature (T) Variation : 

Systems are designed to operate at a nominal supply voltage, but this voltage may vary for many reasons including tolerances of the voltage regulator, IR drops along supply rails, and di/dt noise. Typically the supply is specified at ±10% around nominal at each logic gate.  The supply varies across the chip as well as in time. Speed is proportional to operating voltage VDD and this leads to ±10% delay variations.  As temperature increases, drain current decreases. The junction temperature of a transistor is the sum of the ambient temperature and the temperature rise caused by power dissipation in the package. This rise is determined by the power consumption and the package thermal resistance.   Ambient temperature ranges for parts specified to commercial, industrial, and military standards. Temperature varies across a die depending on which part dissipate the most power. The variation is gradual, so all circuits in a given 1 mm diameter see nearly the same temperature.

Design Corners:

The collective effects of process and environmental variation can be lumped into their effect on transistors: typical (also called nominal ), fast, or slow. When these processing variations are combined with the environmental variations, we define design or process corners. The term corner refers to an imaginary box that surrounds the guaranteed performance of the circuits. The corners are specified with five letters describing the nMOS, pMOS, interconnect, power supply, and temperature,respectively. The letters are F, T, and S, for fast, typical, and slow.  

Basic Nomenclature : 

- NMOS can be slow, typical, fast (S, T, F). 

- PMOS can be slow, typical, fast (S, T, F).  

- Temperature can be hot, typical, cold (S, T, F).

- Vdd can be high, typical, low (F, T, S).

Example of Process corners and their detailed description. Process Corner Label may include NMOS, PMOS, Temp, Vdd.

- TTTT = typical NMOS, typical PMOS, room temp, nominal supply.

- SSSS = slow NMOS, slow PMOS, hot temp, low supply.

- FSSS = fast NMOS, slow PMOS, hot temp, low supply.

Sources of Process Variations:

(i) Lithographic variations : Uniformity of the printed feature sizes depends heavily on the control of the lithographic imaging system. A small vibration in the apparatus can lead to non-uniformity of the critical dimension (CD) of printed lines and significantly change the speed and leakage of CMOS transistors.

(ii) Line Edge roughness : It is the deviation in feature dimension from intended shape. Arises from variations in lithography and etching process.

(iii) Random Dopant Fluctuation : RDF refers to the random microscopic fluctuation of the number and location of dopant atoms in the MOSFET channel region. It causes fluctuations of the transistor electric parameters, such as the threshold voltage (Vt), short channel effect and drain-induced barrier lowering (DIBL).

(iv)Well proximity Effect : Advanced CMOS technology use high  energy implants to form the deep retrograde well . During the  implant process, atoms can scatter laterally from the edge of  the photo-resist mask and become embedded in the silicon surface close to the well edge. As a result well surface concentration changes with lateral distance from the mask edge, over the range of 1um or more. Threshold voltages and other electrical characteristics also vary with the distance of the transistor to the well-edge. This phenomenon is known as the well proximity effect (WPE).

(v) STI & Length Of Diffusion : STI is forming trench and filling it is with nonconducting material to isolate active regions . This filling material exerts  compressive stress to the vicinities, i.e., in diffusion areas. This stress is commonly  referred as STI stress, also called Length of Diffusion (LOD) effect, where the characteristics of a device vary according to the distance of its gate from the diffusion edge. Mechanical stress change free carrier mobility.  Consequently, transistors with the same gate size but a different LOD may have very different speeds.  The stress increases as the channel to STI/Active edge distance decreases.

Impact of Process Variations: 

The MOSFET parameters  parameters  are affected by relevant process steps. A single process step can affect multiple transistor parameters. Decoupling the effects of one variation source from another is extremely difficult.    

(i) Carrier Mobility (μ) :  Mobility is the ability of the carriers (electrons/holes) to travel through the channel of a MOSFET  with an applied electric field.  Mobility of carriers in the channel is impacted by doping  concentration since the it determines the mean free time between collisions. The dose and energy of ion implantation and annealing temperature directly influence mobility since these process steps primarily determine doping  concentrations. Strain engineering of a device channel, either by using local techniques such as Nitride liners and SiGe in source/drains, or global techniques such as SiGe substrates, affect the device mobility. Unintentional stresses  induced due to STI can cause intra-die mobility variations of a few percent depending on the transistor distance to the STI edge.                                                          

(ii) Gate Oxide Capacitance (Cox) : Gate oxide, thicknesses are scaled to atomic level on the order of five atomic layers (10˚A). A small change in one atomic layer can greatly impact on not only the oxide capacitance, but also the threshold voltage and mobility of the MOSFET device. A small variation in the thickness of just one atomic layer would result in a 20% variation in the gate oxide thickness. Controlling this variation is difficult due to physical limitations at this atomic scale. Use of high-K dielectric material as gate oxide results in Moving to a new gate oxide material not only reduces gate leakage currents but also reduces the impact of variability on C ox due to the much larger physical oxide thickness. However, variations in the oxide of "high-k" stacks interfaces are still problematic and can also affect performance.

(iii) Threshold Voltage (Vth): Threshold Voltage is determined by the number and location of dopant atoms implanted in the channel or halo region. Ion implantation is a stochastic process, leading to random dopant fluctuations (RDF) that cause Vth to vary . Impact of statistical distribution become even more significant as device dimension The variations have become large in nanometer processes because the number of dopant atoms is small.

(iv) Transistor Dimensions (W , L) : The saturation current shows that the width and length of a transistor influence the device Current.

Processing steps and related factors like the wafer mask, exposure time, etching process, spacer definition, source/drain implantation and even the environment during the manufacturing process contribute to the overall variation in gate length and width. Any variation in channel length is directly reflected in device delay which is directly proportional to the channel length. Shrinking of the device channel length is physically limited by the patterning wave length ( λ=193 nm for 45 nm Technology node), therefore patterning a very short channel length below this wavelength becomes extremely difficult to control leading to an increase in gate length variation.

(v) ON and OFF Current :   Both on and off current has dependency on L and W. So smallchange in process variation causing variability in L and W finally results in transistor performance variation.

(vi) Yield (Y):  In CMOS yield Y indicates the fraction of products that are operational. It is the probability that a particular product will work. So Failure probability is expressed as X = 1 – Y.  Design techniques and analysis tools are used to minimize the range of variability. Variability more than permissible range cause failure and thus yield reduces. At each node, the dimensions get smaller and thus a constant variability actually means greater percentage of change. Small percentage of variability create larger impact in these dimension.

(vii) Delay:  A change in ON current changes the delay of an inverter by the same fraction. An M-input gate will have up to M transistors that can vary separately. The delay of an N-stage path is the sum of the delays through each stage. If the variations are completely correlated , the delay of the path will have the same variance as the delay of a gate. However, if the variations are independent, the variance reduces by a factor of N × M.

(viii) Energy:  Variation has a minor impact on dynamic energy. Variation has a major impact on static leakage energy. Static leakage energy is exponentially sensitive to threshold voltage. Systematic variation in Vt makes a tremendous impact because all transistors are correlated and the exponential has a long tail.

Analysis Methods for Studying Variability :

Digital circuits are designed in a way so that the circuits should meet the performance specifications such as speed and power consumption under all operating conditions. Statistical fluctuations in the semiconductor fabrication processes leads to undesirable circuit performance.  It is necessary to model manufacturing process variations to predict the device and circuit performance  to minimize the impact of parameter variation on the circuit performance and maximize the yield. There are different general techniques and methodologies used to handle the impact of process variations in circuit design such as, 

    i. Worst Case-corner Analysis

    ii. Monte Carlo Analysis Technique

    iii. Design of Experiments and Response Surface Modelling    (DoE/RSM)

    iv. Sensitivity Analysis

Modeling Variability :

Variations are modeled with : Uniform Distribution ; Gaussian Distribution. 

Uniform distribution refers to a type of probability distribution in which all outcomes are equally likely. Uniform distributions are specified with half-range a.                          

Example : uniform distribution for VDD as 1.0 V ±10%. Here half range is 100. 

Normal distribution also known as Gaussian distribution. A probability distribution that is symmetric about the mean, showing that data near the  mean are more frequent in occurrence than data far from the mean. Normal distributions are specified with a standard deviation X . Processing variations are usually modeled with normal distributions.

Circuit designers commonly treat process variation as a combination of  global variation and local variation. This method lumps all the chip-to-chip  and wafer-to-wafer variations into one global variation component, and the            remaining variations as one local variation component. 

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High-K Dielectrics : VLSI Milestone Episode-1

In this comprehensive article , we delve into several crucial aspects of VLSI (Very Large Scale Integration) technology, providing an in-depth exploration of High-K Dielectrics. These discussions cover significant milestones in VLSI device development, and we shed light on the advantages of Silicon Dioxide (SiO2), which has been a cornerstone in semiconductor manufacturing. We demystify the concepts of Low-K and High-K Dielectrics, explaining why the latter is gaining prominence in modern semiconductor fabrication processes. We also address the pressing question of "Why High-K Dielectric?" by examining its pivotal role in enhancing the performance and efficiency of electronic components. Furthermore, we dive into the intricate domains of dielectric conductance and breakdown, elucidating the critical mechanisms and challenges in this field. The segments titled "Essential Qualities of High-K Dielectrics" provide a thorough breakdown of the key attributes and characteristics that make High-K Dielectrics indispensable in VLSI technology.

Finally, we explore the synergy between High-K Dielectrics and Metal Gate technologies, highlighting their interplay in advancing the capabilities of modern semiconductor devices. This article promises to be an enlightening resource for anyone interested in understanding the significance of High-K Dielectrics in the context of VLSI technology.

Major Device Milestone in VLSI :

Moore’s law has been driving and guiding force for last few decades for enhancement of device performance. To keep up with the pace of scaling, new ways found and introduced, such as :

1. new structure like FinFET, SOI, Nano Sheet FET

2. new material like Strained-Si, High-k dielectric

3. new interconnect material like Cu

Advantages of SiO2 :

Silicon dioxide is the main reason that microelectronics uses Si technology and not another semiconductor. As a semiconductor, Si has average performance, but in most respects SiO2 is an excellent insulator. SiO2 can be made from Si simply by thermal oxidation, whereas every other semiconductor (Ge, GaAs, GaN, SiC…) has a poor native oxide or poor interface with its oxide. SiO2 is amorphous, has very few electronic defects and forms an excellent, abrupt interface with Si. SiO2 can be etched and patterned to a nanometer scale. Its only problem is that it is possible to tunnel across it when very thin.

What are Low-K & High-K Dielectrics?

The dielectric constant, k, is a parameter defining ability of material to store charge. The k value of SiO2 is 3.9 and in si technology it is considered as reference. Dielectrics with k>3.9 are referred as “high”-k and dielectrics with k<3.9 are defined as “low”-k dielectrics. In state-of-art VLSi technology both high- and low-k dielectrics are needed and used for different reasons. 

 Need for high-k dielectric:

- SiO2 has been used as a gate oxide material for decades.

- The thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance, drive current and raising device performance. As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability.

- Use of high-k dielectric instead of SiO2 leads to increased gate capacitance while keeping gate oxide thickness fair enough so that leakage effects are reduced.

Need for low-k dielectric:

-In digital circuits, insulating dielectrics separate the conducting parts (wire interconnects and transistors) from one another. As components have scaled and transistors have gotten closer together, the insulating dielectrics have thinned to the point where charge build-up and crosstalk adversely affect the performance of the device. To reduce parasitic capacitance low-k dielectric is used instead of SiO2.

Why High-k Dielectric ?

Over last few decades scaling of MOSFET dimension has been been viewed as an effective approach to enhance transistor performance as predicted by Moore’s law. Scaling includes Gate Oxide thickness reduction. Reduction in the thickness of silicon dioxide gate dielectrics has enabled increased numbers of transistors per chip with enhanced circuit functionality and performance at low costs.  As we approached sub-45 nm node, the effective oxide thickness (EOT) of the traditional silicon dioxide dielectrics are required to be smaller than 1 nm, which is approximately 3 monolayers and close to the physical limit. Such thin layer of Silicon is prone to high gate leakage current due to the obvious quantum tunneling effect at this scale. To continue the downward scaling, dielectrics with a higher dielectric constant (high-k) are being suggested as a solution to achieve the same transistor performance while maintaining a relatively thick physical thickness.

Dielectric Conductance & Breakdown :

Performance of MOS devices depends on the breakdown properties and the current transport behaviors of the gate dielectric.  Ideally in an MOS structure, the conductance of the dielectric is assumed as zero. However in real world situation under high electric field/ temperature there is some carrier conduction. Tunneling is the conduction mechanism in insulators.  Tunneling is a quantum mechanical phenomenon in which electron wave function can penetrate a potential barrier. 

 

There are 4 different mechanism :

1. direct tunneling, 

2. F-N tunneling,

3. Schottky Emission ,

4. Poole Frankel Emission

Under large bias, tunneling current flows through dielectric. When energetic carriers move through the insulator, defects are generated randomly in the bulk of the dielectric film. If number of defects are high enough to form a  continuous path connecting the gate to the semiconductor, a conduction path is created and dielectric breakdown occurs.

Essential Qualities of High-k Dielectrics:

1. K value, band gap and band offset : To get high capacitance k value must be over 12, preferably 25–30. High-k value means, the dielectrics will have a reasonable physical thickness to prevent gate leakage. The layer must not be too thick to hamper physical scaling when achieving the target EOT. On the other hand, a very large k value is undesirable in CMOS design because they cause unfavorable large fringing fields at the source and drain regions. If a high-k dielectric can replace SiO2, the dielectric thickness (Tk) increases proportionally to keep the same dielectric capacitance. A figure of merit to judge a high-k gate dielectric layer is the equivalent oxide thickness, defined as EOT = (ε1/ε2)T where ε1= 3.9 , ε2 = k value of High-k material, T= High-k dielectric thickness.

2.Thermal stability : In present CMOS processes, the gate stacks must undergo rapid thermal annealing . This requires that the gate oxides must be thermally and chemically stable especially with the contacting materials. Additionally, oxides should not react with water. Among many high k dielectrics, HfO2 has both a high k value as well as chemical stability with water and Si. 

3. Crystallization temperature : Amorphous materials are preferred to crystalline ones, owing to the absence of grains and good diffusion barrier properties. The grains present in the crystalline systems can often be the pathways for dopants diffusion and breakdown. Unlike SiO2, high-k oxides usually have low crystalline temperature and can easily crystallize when subjected to RTA. In particular, HfO2 and ZrO2 crystallize at much lower temperatures at ~400 oC and ~300 oC, respectively. According to the above factors, the approach to improve the crystallization temperature of HfO2 and ZrO2 should be considered. The crystallized HfO2 has a much lower leakage current.

4. Interface Quality : The interface between the high-k dielectrics and Si substrate must have the highest electrical quality and flatness, absence of interface defects, and low interface state density Dit. Bad interface quality can cause high fixed charge density, inducing a large shift in the flat band voltage (Vfb) which severely reduces the performance and reliability of the transistor.

5. O2 and dopant diffusion through the grain boundary

6. Compatibility with the gate electrode

7. Density of interface states comparable to SiO2

8. Low lattice mismatch and similar thermal expansion coefficient with Si 

9. Mobility comparable to SiO2

High -k/Metal Gate:

To continue the downscaling, dielectrics with a higher dielectric constant (high-k) are being suggested. Many candidates of possible high-k gate dielectrics have been suggested to replace SiO2 and they include nitrided SiO2, Hf-based oxides, and Zr-based oxides. Hf-based oxides have been recently highlighted as the most suitable dielectric materials because of their comprehensive performance. One of the key issues regarding new gate dielectrics is the low crystallization temperature. Due ti this reason, it is difficult to integrate them into traditional CMOS processes. To solve these problems, additional elements such as N, Si, Al, Ti, Ta and La have been incorporated into the high-k gate dielectrics, especially Hf-based oxides. For the gate electrode, both poly-Si and different metals have been investigated along with high-κ dielectrics. The combination of a high-κ dielectric and a poly-Si gate is not suitable for high- performance logic applications since the resulting high-κ/poly-Si transistors have high threshold voltages and degraded channel mobility, and hence poor drive current performance.  It has been proposed that the high threshold voltage is caused by Fermi level pinning at the poly-Si/high-κ dielectric interface and that Fermi level pinning is most likely caused by defect formation at that interface. It has been demonstrated both experimentally and theoretically that surface phonon scattering in high-κ dielectrics is the primary cause of channel mobility degradation. Significantly, metal gate electrodes are effective for screening phonon scattering in the high-κ dielectric from coupling to the channel when under inversion conditions. This results in improved channel mobility.

Watch the video lecture here : 

Courtesy : image by www.pngegg.com

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