There are several ways to gain knowledge about embedded systems (VLSI) projects:
Online Courses: There are many online courses available on platforms like Coursera, Udemy, and edX, which can teach you the basics of VLSI design, as well as advanced topics such as FPGA design, system-on-chip (SoC) design, and more.
Joining Forums and Online Communities: Joining forums and online communities is a great way to connect with other people interested in embedded systems and VLSI projects. You can ask questions, share ideas, and learn from others who have more experience.
Reading Books and Articles: Reading books and articles is another excellent way to learn about embedded systems and VLSI projects. There are many books available on VLSI design, FPGA design, and SoC design. Additionally, there are many articles and blog posts available online that cover a variety of topics related to embedded systems.
Hands-on Projects: One of the best ways to learn about embedded systems and VLSI projects is through hands-on projects. You can start with simple projects, like designing a simple digital circuit or building a basic microcontroller-based project, and then work your way up to more complex projects.
Attending Workshops and Conferences: Attending workshops and conferences can provide you with an opportunity to learn about the latest trends and advancements in VLSI design. You can also network with other professionals and learn from experts in the field.
If you're interested in mastering VLSI, here are some steps you can take:
1. Build a strong foundation : VLSI design involves a range of concepts from electrical engineering, computer science, and physics, so it's important to have a solid foundation in these areas. You can start by taking courses in digital and analog circuits, semiconductor physics, programming, and computer architecture.
In this respect see this video for faster ramp up : Click Here
2. Learn VLSI design tools: VLSI design involves the use of specialized software tools such as Cadence, Synopsys, and Mentor Graphics. You can start by learning the basics of these tools through online tutorials, courses, or textbooks. There Are Open Source Tools to Lean at free of cost.
But before starting, your linux training must be completed , as all the professional VLSI tools work in linux ONLY : Click Here
3. Take VLSI design courses: Look for courses that offer in-depth coverage of VLSI design concepts and techniques, such as transistor-level design, layout design, timing analysis, and verification. You may also consider taking courses in related fields such as computer architecture, signal processing, and embedded systems.
4. Join VLSI design projects or internships: Hands-on experience is crucial for mastering VLSI design. You can look for opportunities to work on VLSI design projects in your university or industry. You may also consider applying for internships in semiconductor companies or VLSI design firms.
You can find Internship by yourself in this way : Click Here
5. Read research papers and attend conferences: To stay up-to-date with the latest developments in VLSI design, you should read research papers published in top conferences and journals such as the International Symposium on VLSI Design and Test (VDAT), IEEE Transactions on VLSI Systems, and ACM Transactions on Design Automation of Electronic Systems.
6. Network with VLSI professionals: Attend industry events, meetups, and conferences to network with professionals in the VLSI field. You can also join online communities such as LinkedIn groups or forums to connect with other VLSI enthusiasts and experts. You must open a LinkedIn Account for this purpose.
Remember, mastering VLSI design requires a combination of theoretical knowledge, practical experience, and passion for the field. With dedication and hard work, you can become a skilled VLSI designer and contribute to the advancement of the electronics industry.
Firstly, congratulations on internship experience ! You have gained valuable skills and knowledge during this time, which can be leveraged to find your next job.
Here are some suggestions to help you in your job search:
Leverage your network: Reach out to your former colleagues, classmates, professors, and other professionals in your field. Let them know that you are searching for a job and ask if they have any leads or know of any opportunities.
Apply for entry-level positions: Many companies offer entry-level positions for recent graduates and individuals with little to no work experience. Even if the job listing specifies that they prefer some experience, you should still apply if you meet the other qualifications.
Look for intern-to-hire programs: Some companies offer intern-to-hire programs, which can be a great way to transition into a full-time position. Check with Synopsys to see if they offer such a program or if they know of other companies that do.
Highlight your skills and accomplishments:In your resume and cover letter, focus on the skills and accomplishments you gained during your internship. Including your internship experience in your CV can help you showcase your skills and abilities to potential employers. Here are some tips on how to effectively include your internship experience in your CV:
Start with a clear and concise summary: Begin your CV with a brief summary that highlights your key skills, experience, and achievements, including your internship experience. This will give potential employers a quick overview of your qualifications.
Use a reverse-chronological format: List your internship experience in reverse-chronological order, starting with the most recent one. This will make it easy for employers to see your most recent experience first.
Include relevant details: For each internship, provide the company name, job title, location, and dates of employment. Also, include a brief description of your responsibilities and accomplishments during the internship. Be sure to highlight any skills or accomplishments that are relevant to the job you are applying for.
Quantify your achievements: Where possible, use specific numbers or data to demonstrate your achievements during your internship. For example, if you helped increase website traffic or social media followers, include the percentage of growth you achieved.
Use action verbs: Begin each bullet point with an action verb to describe your accomplishments during your internship. This will make your CV more dynamic and engaging.
Tailor your CV to the job description: Make sure to tailor your CV to the specific job you are applying for. Highlight the skills and experience that are most relevant to the job, and use keywords from the job description.
Remember to keep your CV clear, concise, and focused on your achievements and skills. By effectively highlighting your internship experience, you can demonstrate your value to potential employers and increase your chances of getting hired.
Keep learning: Consider taking online courses or attending webinars to keep learning and improving your skills. This will show potential employers that you are proactive and dedicated to your field.
Remember, finding a job can be a lengthy process, but don't get discouraged. Stay positive, keep networking, and keep applying to jobs. Good luck!
Approaching companies for internships or jobs in VLSI can be done through several steps:
1. Identify the companies you are interested in: Research companies that are involved in VLSI design and manufacturing, and make a list of those that interest you. You can use resources such as online job boards, company websites, or industry associations to find potential employers.
2. Tailor your resume and cover letter: Customize your resume and cover letter to highlight your skills and experience that are relevant to VLSI. Be sure to emphasize any coursework, projects, or internships you have completed that demonstrate your knowledge and skills in this field.
3. Network: Connect with individuals in the VLSI industry through social media, professional associations, and alumni networks. Networking can help you learn about job openings and make valuable connections. Open a LinkedIn Account for professional networking.
4. Apply for internships or jobs: Apply for internships or jobs through the company's website or through job boards such as LinkedIn, Indeed, or Glassdoor. Be sure to follow the application instructions carefully and provide all required materials.
5. Follow up: After submitting your application, follow up with the company to express your interest and ask about the status of your application. This demonstrates your enthusiasm for the position and can help you stand out from other candidates.
During this phase deal with the stress in this way :Click Here
Overall, approaching companies for internships or jobs in VLSI requires preparation, networking, and persistence. By tailoring your resume and cover letter, connecting with industry professionals, and applying for positions, you can increase your chances of landing an internship or job in this exciting field.
Analog VLSI design, digital VLSI design, and analog-digital mixed-signal (ADMS) design are all important aspects of modern integrated circuit (IC) design. Each of these design approaches has its unique features and design challenges. Here's a brief comparison of the three:
Analog VLSI Design: Analog VLSI design deals with the design of analog circuits that perform continuous signal processing tasks. Analog circuits are used in a wide range of applications, including signal amplification, filtering, and power management. The design of analog circuits requires a deep understanding of semiconductor physics and device behavior, as well as an ability to deal with non-linearities and noise. Analog VLSI designers must also be skilled in layout design, as physical layout can have a significant impact on circuit performance.
Digital VLSI Design: Digital VLSI design is concerned with the design of digital circuits that perform discrete signal processing tasks. Digital circuits are used in a wide range of applications, including computation, communication, and control. Digital circuits are based on binary logic and are designed using high-level hardware description languages (HDLs) such as Verilog or VHDL. Digital VLSI designers must be skilled in digital logic design, timing analysis, and verification, as well as physical layout.
Learn more about Analog and Digital Physical Design :Click Here
Analog-Digital Mixed Signal Design: ADMS design involves the integration of both analog and digital circuits on a single chip. This approach is becoming increasingly important as more and more applications require both analog and digital signal processing capabilities. ADMS designers must be skilled in both analog and digital design, as well as the techniques required to interface between the two domains. ADMS design is particularly challenging because the performance of analog circuits can be affected by digital circuitry on the same chip, and vice versa.
Learn More About , Analog and AMS VLSI Domains : Click Here
In summary, analog VLSI design, digital VLSI design, and analog-digital mixed-signal design are all important aspects of modern IC design. Analog VLSI designers focus on continuous signal processing tasks, digital VLSI designers on discrete signal processing tasks, and ADMS designers must be skilled in both analog and digital design. Each of these approaches has its unique features and design challenges, and the choice of approach depends on the specific requirements of the application.
Many times we have faced a common question from freshers whether it is possible to get a VLSI job through off-campus placement. Yes, it is possible, although it may require more effort and time on your part to find suitable job openings and apply for them.
Here are some tips to help you in your job search:
1. Build your skills: Make sure you have a strong foundation in VLSI design, verification, and testing. Keep yourself updated with the latest tools and methodologies used in the industry. Free VLSI Skill Training for you:
2. Create a strong resume: Highlight your relevant coursework, projects, and any relevant experience you have. Tailor your resume to the specific job you are applying for.
3. Network: Attend industry events, job fairs, and connect with VLSI professionals on LinkedIn. This can help you learn about potential job openings and get your foot in the door.
4. Apply to relevant job openings: Look for job openings at companies that specialize in VLSI design, semiconductor manufacturing, or electronic design automation (EDA) software. Apply to multiple opportunities and make sure to follow up with each company.
5. Prepare for interviews: Practice common interview questions and be prepared to talk about your relevant skills and experience. Show your enthusiasm for VLSI and highlight any relevant coursework or projects.
Watch this video for further guidance :
It's important to note that getting a VLSI job through off-campus placements may take more time and effort compared to on-campus placements or through referral. However, with persistence and a focused job search strategy, you can find exciting and rewarding job opportunities in this field.
In the article, an array of pivotal topics within the realm of VLSI have been meticulously explored. The discourse embarks on a journey through the significant milestones achieved in VLSI, particularly delving into the intricate domain of Multiple Patterning techniques. Within this realm, a thorough investigation into Lithography is conducted, unraveling its various types and shedding light on the indispensable concept of Multi-Patterning. The imperative necessity for Multi-Patterning in modern semiconductor fabrication processes is scrutinized, elucidating its role in overcoming the constraints posed by traditional lithographic methods. Furthermore, the discourse navigates through the complexities of Phase Shift Mask and Optical Proximity Correction, unveiling their critical roles in enhancing lithographic precision. Moreover, the session ventures into the intricacies of Layout Decomposition, Double Patterning, and even explores advanced techniques like Triple and Quadruple Patterning, illuminating the evolving landscape of VLSI fabrication methodologies.
VLSI Milestone & Multiple Patterning:
Moore’s law has been driving and guiding force for last few decades for enhancement of device performance. As minimum feature size has reduced, CMOS process has been greatly challenged by patterning technique of such miniature device dimension. Due to the fundamental optical resolution limit, the 193nm immersion lithography can only achieve the minimum pitch about 80nm using single exposure. To continue the technology scaling in 22nm, 14nm, and beyond with the 193nm lithography, multiple patterning technologies have been developed to obtain finer pitches. Multi-patterning became a necessary step as next-generation extreme-ultraviolet (EUV) lithography tools were not yet ready for production.
There are two main types of multiple patterning lithography :
(i) based on repeated process,
(ii) based on self-aligned spacer process.
Lithography:
Lithography is the process of transferring patterns of geometric shapes in a mask to a thin layer of radiation sensitive material/resist covering the surface of a semiconductor wafer.
An IC fabrication facility requires a clean room, particularly during lithography process. Dust particles settling on semiconductor wafers and lithographic masks can cause defects in the devices. Performance of a lithographic exposure is determined by three parameters: (i) resolution, (ii) registration, (iii) throughput.
Resolution is defined to be the minimum feature dimension that can be transferred with high fidelity to a resist film on a semiconductor wafer. Registration is a measure of how accurately patterns on successive masks can be aligned or overlaid with respect to previously defined patterns on the same wafer. Throughput is the number of wafers that can be exposed per hour for a given mask level and is thus a measure of the efficiency of the lithographic process
Different Types of Lithography:
Optical Lithography : Majority of lithographic equipment for ICfabrication is optical equipment using light in the ultraviolet range of the EM spectrum.
(a) DUVL : Uses controlled 254–193-nm light to create pattern.
(b) EUVL : Uses 13.5 nm light to create intricate patterns on silicon wafers. EUVL wavelength is close to X-ray. EUV lithography reduces the number of mask count, although more expensive than other systems for microchip lithography.
X-ray lithography: Uses X-rays, X-ray sensitive special resist, a mask composed of an X-ray absorbing material
patterned on a thin membrane that is X-ray transparent, often made of low atomic number elements like Si/B.
Ion Lithography :Ion lithography can achieve higher resolution than optical, x-ray, or electron beam
lithographic techniques because ions undergo no diffraction and scatter much less than electrons.
E- Beam Lithography (EBL) : Direct writing lithographic process. Uses a focused beam of electrons to form patterns. E-beam lithography is not suitable for high-volume manufacturing because of its limited throughput.
Depending on exposure method 3 types of printing are there :
(i) contact printing
(ii)proximity printing
(iii) projection printing
What is Multi-Patterning?
A class of technologies developed for photo-lithography to enhance the feature density. A single lithographic exposure may not be enough to provide sufficient resolution. Multiple patterning is a technique that overcomes the lithographic limitations in the chip-manufacturing process. Single exposure, 193nm wavelength lithography reached its physical limit at 40nm half-pitch. MP enables chipmakers to image IC designs at 20nm and below.
There are two main categories of Multi Patterning:
(i) pitch splitting and (ii) spacer.
Pitch splitting includes Double and Triple Patterning.
Rayleigh criterion specifies the minimum separation between two light sources that may be resolved into distinct objects. Critical dimension or resolution is defined as :
Feature size is constantly dropping to lower value. CD can be reduced by :
1. Increasing NA :NA cannot be increased beyond 0.93. It will reduce the depth of focus and sharpness of the image printed become less
2.Decreasing k1 :Reducing k1 is a good option. In single patterning k1 is restricted to a minimum of 0.25 and cannot go beyond that . Using multiple patterning decreases k1 from 0.25.
3.Decreasing λ : Reducing λ below 193 nm results in a lot of technical issues cost, risk and throughput.
If a pitch could not be achieved in a single lithography step, the design is split over two lithography layers so that the minimum pitch is relaxed with respect to the target pitch.
In this way the effective k1 of the total process resulting from combination of the two lithography steps can drop below the 0.25 for a single patterning process. The increased pitch size enables higher resolution and better printability.
Phase Shift Mask :
PSM is used to alter the phase of the light passing through some areas of the mask. Phase change modifies the way light is diffracted. As a result defocusing effect reduces. The downside of using phase-shift techniques is that such masks are more difficult and expensive to make.
Optical Proximity Correction:
A photolithography enhancement technique. Used to offset the optical proximity effect. Photomask patterns transferred onto a photoresist under insufficient resolution develop inaccuracies. In OPC, mask geometry is modified to compensate for pattern transfer non-idealities.
Layout Decomposition :
Splitting one layer into multiple masks. For MPL , one of the most fundamental problems is to decompose the layout into a specific number of masks, such that each mask should be able to manufactured under current lithography.
When there is not enough distance between two patterns, different masks should be used to print them. It is possible that given masks are not enough to print specific features, which results in conflicts. Thus, one basic objective for layout decomposition is to avoid conflicts.
Double Patterning:
Double patterning is a technique used in the lithographic process for sub 30 nm process. This process requires increased mask and lithography costs. DP is an effective way to counter the effects of diffraction in optical lithography. Such situation occurs because the light source has wavelength of 193 nm and the process node is fraction of that. Diffraction effects makes it difficult to produce accurately defined deep sub-micron patterns using existing lighting sources and conventional masks. Sharp corners and edges become blurs, and some small features on the mask won’t appear on the wafer at all.
Triple patterning is quite silimilar like double patterning. In this process polygons are partitioned into three masks. Advantage of triple patterning over double is that it is denser. Although use of 3 masks create misalignment. TP refers to the litho-etch-litho-etch-litho-etch (LELELE). LELELE requires three separate lithography and etch steps to define a single layer. Provides a reduction in pitch, increase in expense because of increased process steps.
Self-aligned quadruple patterning (SAQP) is the most widely available technology used for patterning feature pitches less than 38 nm. It is already being used to pattern the fins of FinFETs and DRAM. This process allow lines originally drawn 80 nm apart to generate lines which are ultimately 20 nm apart . Able to do high volume lithography compared to EUV , which has 13 nm resolution. SAQP process steps are shown below.
The article delves into crucial aspects shaping Very Large Scale Integration (VLSI) technology, notably focusing on milestones and advancements in multi-level metalization. The discussion traverses through the intricacies of metalization, particularly emphasizing its multi-level nature and the components integral to its composition. Noteworthy attention is dedicated to exploring interconnect materials, including the prevalent use of aluminum (Al) and the emerging dominance of copper (Cu), delving into their respective reliability factors. The discourse further delves into the intricacies of the single/dual Damascene processes, distinguishing between aluminum and copper interconnects while scrutinizing their comparative advantages. Additionally, the article video provides valuable insights into low-k intermetal dielectrics, elucidating the underlying physics governing their functionality and exploring various materials characterized by low dielectric constants.
VLSI Milestone & Multi Level Metallization:
Moore’s law has been driving and guiding force for last few decades. With progressing node circuit complexity has increased. Reduced dimension has made short channel effect, parasitic effect more severe. To keep up with the pace of scaling, new material, new device structure was found and introduced. Higher package densities and design flexibility was achieved by increasing interconnect layers. To increase circuit performance different materials incorporated at different part of total interconnect network. Research led us to new inter-metal dielectric layer or low- k dielectric layer.
Metallization:
Conductive films provide electrical interconnection among devices as well as the outside. Three categories : gate, contact and interconnect.
Polysilicon and Silicide are frequently used for gate connection , Al/Cu are used as contact and second-level interconnection to the outside. In some cases, a multiple-layer structure involving a diffusion barrier is used. Titanium /platinum/ gold or titanium / palladium / gold is useful in providing reliable connection to external components.
Circuit speed is controlled by the resistance and capacitance of the interconnect. Metallization is deposited by either physical vapor deposition (PVD) or chemical vapor deposition (CVD).
Desired properties of the metallization for ICs:
1. Low resistivity , easy to form and easy to etch for pattern generation
2. Should be stable in oxidizing ambients and oxidizable
3. Mechanical stability, good adherence, and low stress
4. Surface smoothness
5. Must be stable throughout processes including high temperature sinter, dry/wet oxidation, gettering, passivation, and metallization
6. No reaction with final metals
7. Should not contaminate devices, wafers, or working apparatus
8. Good device characteristics and lifetimes
9. For window contacts - low contact resistance, minimal junction penetration, and low electro-migration
Multi Level Metallization:
RC Time Delay : As technology progresses, Ls decreases. RC delay increases.
Length of wire must be kept small – Multi Level Metallization
Lower resistivity metal for interconnect wiring – Cu Interconnect
Lower dielectric constant material for the interlayer dielectric - Low-K
Contact Resistance : Low contact resistance to semiconductor device
Immunity to EM : reliable long-term operation
State-of-art ICs have millions of transistors and connecting them all to some voltage and current supply without wires crossing is a real challenge. 3-D network of interconnections is called Multi Level Metallization. Multi-level metallization increases interconnect capacity and reduces resistance and capacitance.
Stretches over several planes and isolated by the insulating dielectric layers. Interconnected by the wiring through the holes in the dielectric planes.
Benefit of Multi Level Metallization:
- Reduced interconnection lengths and reduced RC,
- Higher package densities and design flexibility
Components of Multi Level Metallization:
Components of Multi Level Metalization Circuit are:
(i) Interconnects,
(ii) Contacts,
(iii) Vias,
(iv) Intermetal Dielectric ,
(v) Passivation.
Active devices are electrically connected to each other. They are connected to the outside world through their I/P and O/P on bonding pads. Contact is connection to source, drain or poly. Vias are connections between interconnect levels. Interconnects are separated from each other by dielectric layers. Vias connect interconnects through these layers. These components are part of the metallization/backend/BEOL. Local interconnects are the first/lowest level of interconnects. They are small and short and connect gates, sources and drains. Poly Si, Silicide, TiN, W (Tungsten) can act as local interconnect. Local interconnects can afford to have higher resistivities since they do not travel very long distances. They must be able to withstand higher processing temperatures. Global interconnects are usually made of Al/Cu. They are above the local interconnect level. Global interconnects are thick, long, and widely spaced. They travel longer distances, between different devices and different parts of the circuit, and therefore are always metals with lower resistivities. After completion of metallizationa passivation layer is formed to protect the internal semiconductor devices. The passivation layers are typically formed with deposition of an oxide layer and a nitride layer.
Interconnect Material : Aluminium(Al)
Aluminum interconnects were used as the standard for a long time in chip-making. In the late 1990s, chip-makers switched to Cu.
=>Advantages of Aluminium :
- It is a good conductor
- It can form mechanical bonds with silicon
- It can form low resistance, ohmic contacts with heavily doped n-type and p-type silicon
- Corrision resistant
=>Disadvantages of Aluminium :
- Low melting point
- Junction Spiking
- Electromigration
- Stress migration
=>Junction Spike :
Use of pure aluminum leads to a diffusion of siliconinto the metal. Si reacts with the metallization at only 200–250 °C. This diffusion of Si causes cavities at the interface of both materials which are then filled by Al. This leads to spikes which can cause short circuits if they reach through the doped regions into the silicon crystal beneath. Size of these spikes depends on the temperature at which the Al was deposited. To avoid spikes a deep ion implantation can be introduced at the location of the vias. Thus the spikes do not reach into the substrate. An alloy of aluminum and silicon can be used (silicon 1–2 %). Since Al now already contains silicon there will be no diffusion out of the substrate. A barrier of different materials such as titanium, titan nitride or tungsten is deposited as barrier layer.
=>Electromigration:
Electro-migration is the movement of atoms in a metal film due to momentum transfer from the electron carrying the current. Under high current density condition metal atom movement creates void in some region and metal pileup or hillock in the other regions. As a result either open ckt. or short ckt. happens in interconnect networking. A common practice to prevent Em is to use an i.e. alloying with copper (Al with 0.5%Cu).
=>Stress Migration:
Due to difference between coefficient of thermal expansion for Al and Si. At high temperature compressive stress get created in Al. Movement of Al occurs along grain boundaries. Whole grains of Al pushed upward forming hillocks. Tensile stress creates voids, crack i.e. electrical open. Compressive stress creates hillocks i.e electrical shorts. Rough surface topography making lithography and etch difficult.
Interconnect Material : Copper(Cu)
Use of diffusion barriers and adhesion promoters :
Cu has poor adhesion properties. An adhesive material is required which will provide stability across interface. Silicides such as TiSi2 can be used as adhesion promoter. TiSi2 doesn’t have good barrier properties. To stop reaction between metals (W, Al etc) and Si or between two layers a barrier layer is used. TiN has contact resistance higher barrier than TiSi2. Bilayer structure of TiSi2 /TiN is used as adhesion promoter and diffusion barrier.
Unlike Al metallization, Cu cannot be easily patterned by reactive ion etching (RIE). Hence, to fabricate Cu interconnects, a different process flow which is called “damascene” process has been developed, including “single damascene” and “dual damascene” processes.
Single/Dual Damascene Process :
In Single Damascene process first inter layer dielectric layer is deposited and via is etched out. Next via is filled with Cu. Excess Cu is removed by Chemical mechanical Polishing (CMP). After that trench is etched out from ILD and filled with Cu. Excess Cu again removed using CMP.
In Dual Damascene process inter layer dielectric layer is deposited and after that trench and via both are etched. After that Cu is filled and excess Cu is removed using CMP. In
Dual Damascene process less step and time is required. Depending on whether trench or Via which one is etched earlier the process is named as (i) Via first or (ii) Trench first.
Low K Inter Metal Dielectric:
Lower-k dielectrics are grouped as ,(i) Ultralow-k (k < 2.2-2.4) or (ii) low-k (2.4 < k < 3.5). These materials can be deposited either by a spin-on route (spin-on dielectrics or SODs) or by a chemical vapor deposition (CVD) or plasma-enhanced PECVD technique. Their final properties are influenced by both the deposition method and post deposition treatment such as anneals or chemical treatments.
Physics of Low-K Dielectric:
Dielectric constant k is also also called relative permittivity εr. K =(Permittivity of a substance/ Permittivity of free space) A material having polar components, has an increased dielectric constant. These polar chemical bonds are represented as electric dipoles. When external electric field applied, the dipoles align with the field. Electric field of every dipole is added to the external field. A capacitor with a dielectric medium of higher k will hold more electric charge at the same applied voltage. Therefore C will be higher.
Si-O bonds replaced with less polar Si-F/Si-C bonds.
Using virtually all nonpolar bonds: C-C/C-H.
Density of a material can be reduced increasing free
volume through rearranging the material structure or introducing porosity. Porosity can be constitutive/subtractive.
Constitutive porosity refers to the selforganization of a material. After manufacturing, such a material is porous without any additional treatment. Subtractive porosity involves selective removal of part of the material.
This can be achieved via an artificially added ingredient .
Different Low-K Material:
Classification of Low-K material:
(i)Si - containing , (ii) non-Si-containing.
2 types of Si-containing materials:
(i) silica-based , (ii) SSQ-based.
To reduce the k value of silica, some oxygen atoms
are replaced with F, C, or CH3.
Addition of CH3 introduces less polar bonds and
also creates additional free volume.
The first low-k materials were F- or C-doped SiO2.
In SSQ , Si and O atoms are arranged in a form of cube.
This creates free volume in the center of the cube,
decreasing the material’s density and K value. The cubes can be connected to each other through
oxygen atoms.
HSSQ - some cube corners are terminated by hydrogen
