Special Standard Cells in UPF. Episode : 3

In this article , we delve into several key topics related to UPF and its interaction with standard cells. We begin by discussing the relationship between UPF and corresponding standard cells, outlining how they work together in power management. Next, we compare UPF with standard cells, providing insights into their respective roles and functionalities. The video then details the specific UPF commands associated with various types of cells, including header/footer switch cells, isolation cells, retention cells, and level shifter cells, explaining how each command facilitates effective power management. Additionally, we cover the placement of these standard cells within power domains, illustrating the strategic considerations for optimizing power distribution. Through this comprehensive discussion, readers gain a thorough understanding of how UPF and standard cells integrate to enhance power efficiency in chip design.

UPF & Standard Cells:

We will talk about four types of standard cells : Switch Cell, Isolation Cell, Retention Cell and Level Shifter Cell and their UPF commands..These are special types of standard cells. 

UPF vs Standard Cells Mapping:

create_power_switch : Header/Footer Switch Cells

set_isolation : Isolation Cells

set_retention : Retention Cells/Retention Flops

set_level_shifter : Level Shifter Cells

Power Switch Cells:

To turn OFF power supply to a power domain for a particular time of operation, we need a power switch to cut the power supply(VDD/VSS) to the domain. The create_power_switch command defines an instance of a power switch in the power domain. The switch is created within the scope of the power domain. The switch is either turned on or off as per the requirement.

Isolation Cells:

When Power Gating method is applied to a design, in a particular mode of operation, we might end up with few ON domains and few OFF domains. If the outputs of the Shutdown domain are connected to the Active Part of the design, then it might lead to Invalid Signal Transmission and crowbar current as a result. To avoid this, an Isolation Cell is placed on the output nets of Switched OFF domains interacting with an Active Portion of the Design.

Isolation UPF Command:

- The set_isolation command specifies the design elements in the domain to isolate using the specified strategy.

- isolation_supply_nets can specify a single power net, a single ground net, or both.

- If only an isolation power net is specified, then automatically the primary ground serves as the isolation ground. 

- If only an isolation ground net is specified, then the primary power net serves as the isolation power. 

-At least one of -isolation_power_net or                                   -isolation_ground_net shall be specified, unless                     -no_isolation is specified.

Retention Cells/Flops:

A retention cell is used to retain the data required in shut down power domain. A retention cell consists of a flipflop and a save latch and has two control signals, SAVE and RESTORE. SAVE signal indicates when the data should be saved in the latch, which is just before Switching OFF the power. RESTORE signal tells when the data stored in latch should be restored which is when the domain gets back to active state.

Retention UPF Commands:

- The set_retention command specifies which registers in the power domain need to be retention registers.

- Only the registers implied in the elements list shall be provided retention capabilities.

- At least one of -retention_power_net or - retention_ground_net shall be specified.

- If only -retention_power_net is specified, the primary ground net shall be used as the

retention ground supply.

If only -retention_ground_net is specified, the primary power net shall be used as the retention power supply.

If both are specified, then these options specify the supply nets to use as the retention power and ground nets.

Level Shifter Cells:

When two blocks powered with different voltage levels interact with each other, invalid signal transmissions and crowbar current generation may take place. To avoid this, level shifter cells are placed between the blocks with distinct voltage values. Level shifter cell can convert a high voltage level to low voltage level between the domains.  Level shifters are the placed on signals that have sources and sinks operating at different voltages.

Level Shifter UPF Command:

- The set_level_shifter command can be used to set a strategy for level shifting during implementation.

- Level shifter rule can be low_to_high/high_to_low or both .

- If low_to_high is specified, signals going from a lower voltage to a higher voltage get a level shifter when the voltage difference exceeds that specified by threshold .

-If high_to_low is specified, signals going from a higher voltage to a lower voltage get a level shifter when the voltage difference exceeds that specified by threshold .

If both is specified, it is equivalent to having specified both rules in the strategy.

Types of Level Shifter Cells :

Level Shifter POSITION defines where the level shifter cells are placed in the logic hierarchy. All necessary supplies need to be available in the specified location.

Self : the level shifter cell is placed inside the model/cell being shifted.

Parent : the level shifter cell is placed in the parent of the cell /model being shifted.

Sibling : a new sibling is created into which the level shifter cells are placed.

Fanout : level shifter occur at all fanout locations (sinks) of the port being shifted.

Automatic : the implementation tool is free to choose the appropriate locations.

Standard Cell Placement:

Watch the video lecture here:

Courtesy : Image by www.pngegg.com

Read More

Power Domain in UPF. Episode : 2

In this article, we explore several crucial aspects related to power domain concepts in UPF. We begin by explaining the fundamental power domain concept, providing a clear understanding of its importance in power management. The discussion then moves to the implementation of a power domain with a single hierarchical instance, elaborating on how it functions within a design. We also cover the creation of power domain instances with child elements, highlighting the complexities and benefits of such configurations. Additionally, we delve into the process of creating further hierarchy within power domains, illustrating how designers can manage and optimize power distribution effectively. This article includes a detailed explanation of the UPF power domain creation command, accompanied by a practical example to demonstrate its application. Lastly, we address the commands for creating UPF power ports and power nets, emphasizing their roles in establishing robust power connections within the design framework.

Power Domain (PD) Concept : 

Blocks which can be operated with the same power supply are identified & tied together. This forms a Power Domain. A particular power domain can be completely kept OFF or ON irrespective of the neighboring block. A power domain contains a collection of design elements that share a primary power and ground supply net. The logic hierarchy level where a power domain is created is called the scope of the power domain. Any design elements that belong to a power domain are said to be in the extent of that power domain.

PD with Single-Hierarchy-Instance:

In this case the only element in the power domain is A, which could be a Hard Macro or a Soft IP (e.g., an instance of a Verilog module).

Instance with Child Elements :

Here the scope of the power domain is the same as the extent, and the power domain is contiguous. 

- Supply port on A is created using  create_supply_port command .

- Then supply port is connected to supply net using connect_supply_net command.

- create_supply_net command applied explicitly in scope A and implicitly in U1 and U2 .

- Supply ports implicitly created on U1 and U2 to connect all the supply nets together.

PD-A contains U1/UA and U2:

Here the topology of the logic design is even more complex.  Here the power domain consists of U1/UA and U2. The two instances in the same power domain which are neither contiguous nor adjacent in the logic design, resulting in a non-contiguous power domain.

In this case, when the create_supply_net command is executed to create a supply net in the power domain, the supply net is explicitly created in A using the name specified in the create_supply_net command.

Supply ports and supply nets are also implicitly created in U1, U1/UA, and U2. The supply net in U1 connects only to the port on U1 and U1/UA.

Power Domain Creation Command:

A power domain is created using UPF command :

create_power_domain <domain_name> [-elements list] [-include_scope] [-scope instance_name]

<domain_name> The new power domain; this shall be a simple (non-hierarchical) name.

[-elements list] Use this set of design elements in the power domain.

[-include_scope] Include the scope of the domain in the extent of the power domain.

[-scope instance_name] Create the power domain within this logic hierarchy scope.

Power Domain : Example

Power Domain : Example

Power Ports & Power Nets:

- Power comes from main power sources through I/O pad-ring via Power Port.   

- The Supply Nets are used to connect Power Ports to Power Pins of each of the cells.

- create_supply_port <port_name> [ -domain domain_name ] [ -direction < in | out >]

- create_supply_net <net_name> -domain <domain_name> [-reuse] [-resolve <unresolved | one_hot | parallel>]

-reuse Extend net_name as a supply net within domain_name. No new nets are created.

-resolve <unresolved | one_hot | parallel> A resolution mechanism which determines the state and voltage of the supply net from the state and voltage values supplied by each of the individual switches. The default is unresolved.

Watch the video lecture here :

Courtesy : Image by www.pngegg.com

Read More

What is Unified Power Format ? Episode : 1

In this article, we delve into several critical aspects of UPF in the context of modern CHIP design. We start by exploring the role of UPF in today's CHIP design scenario, providing insights into its importance and application. The discussion then moves to the integration of UPF within SOC design, detailing how it is strategically placed and utilized. We also offer an in-depth explanation of what UPF is, clarifying its fundamental concepts and functionalities. Furthermore, we examine the three major types of UPF annotations, shedding light on their specific purposes and usages. Key standard UPF terminologies are explained to ensure a clear understanding of the language and practices involved. Additionally, we highlight the integration of UPF across various design stages, illustrating its significance throughout the design process. Finally, we identify and describe the four major types of UPF commands, explaining their roles and applications within the design framework.

The Scenario of Today’s CHIP :

Above diagram represents a state-of art chip. Power Management Block, Digital Block, Macro, Analog Block etc are part of it. Digital and Analog block runs on different Vdd. The Power Grid in ASIC provides power to turn on/off any VLSI chip. Power Delivery Network Carries Power towards the leaf cell such as : Standard Cells, IPs-Block or Macro-Blocks. The Power Management Unit (PMU) resides in between leaf cells and the Power Grid to control the flow of power. PMU Decides and Manages the power consumption through segregation known as Power Domains. Blocks which can be operated with the same power supply are identified & tied together. This forms a Power Domain. A particular power domain can be completely kept OFF or ON irrespective of the neighboring block. A power domain contains a collection of design elements that share a primary power and ground supply net. The logic hierarchy level where a power domain is created is called the scope of the power domain. Any design elements that belong to a power domain are said to be in the extent of that power domain. Isolation cells, Level shifter , Power switches are part of the whole system and they are very much instrumental to maintain the power domain. RTL coding is unable to express the power description of the system. UPF is used to describe power requirement of the chip.

UPF & Today’s Design :

The above diagram shows that entire design is described in two ways where functional description is done by Verilog, VHDL, Verilog AMS, VHDL AMS depending on the functional block of the system. Power intent or power description of the circuit is expressed by either UPF or CPF. Here we will talk about UPF only.

What is UPF :

UPF is an abbreviation of Unified Power Format owned by the Accellera. Any HDL do not have a way to define the power distribution/intent of a Design. UPF acts as a missing link here in filling the gap. UPF extends the logic design by adding power-aware functionality. It Annotates power distribution and power control intent. It can be defined from abstract level. It defines no routing or layout information. A UPF specification can be included with the other deliverable of an IP block. UPF contributes to Power Aware Verification.

Types of UPF Annotation:

There are three types of annotation Power Supply, Power Control and Protection. Supply Net, Supply Set, Power State are three annotation that comes under Power Supply. Power Switch is a UPF annotation that comes under Power Control. Protection can come from Level Shifter and Isolation.

Benefit of using UPF:

To allow interoperability across different EDA vendors. UPF supports Tcl syntax and semantics. UPF is constantly being evolved. At synthesis stage, special management cells are inserted in the design as per in UPF intent. At Physical Design/Implementation stage, few cells like clamp cells are added into the design as per UPF intent. 

Standard UPF Terminologies:

Design Element: Is an instance of a Verilog module , VHDL entity or a library cell. Design element is often abbreviated to element.  

Design Object (a.k.a object): A design object is any object inside the logic hierarchy. 

Design objects include : wires, registers, switches, ports, supply nets, design elements etc.

Extent: The set of design elements that comprise a power domain. 

Standard UPF Terminologies:

Power Domain: A collection of design elements that share a primary supply. A power domain may also have additional supplies, including retention and isolation supplies.

Power State Table: A table that captures the legal combinations of power states for a set of supply nets.

Scope: A particular design element in the logic hierarchy .

Regulator: A design element that takes a set of input supply nets and acts as the source for a set of output supply nets.

Current Instance: The instance specified by the set_scope command.

Design Stages & UPF: 

The above infographics shows the stages where UPF is used in SoC design flow. In SoC design at the stage of RTL design HDL and UPF commands are used. At sythesis level Gate Level Netlist and UPF is used. AT  Place and Route level we have post layout netlist or PG netlist along with UPF. Finally we have LEC (Logic Equivalence Check) , Simulation and at each stage correctness of UPF is checked throughout the design.

Type of UPF Commands:

UPF is very similar to TCL command in syntax or semantics although not very close to basic TCL commands. These are advance version of the same developed for UPF. 

There are four types pf UPF commands:

1. Power Intent Command

2. SAIF
3. Query Command

4. Test-Bench Command

Watch the video lecture here:

Read More

Clock Tree Synthesis in VLSI

This article covers a broad range of topics related to clock tree synthesis (CTS) in VLSI design flow. The discussion begins with an introduction to CTS and its significance in VLSI design, followed by an overview of pre- and post-CTS diagrams. The various levels involved in the CTS process and the CTS methodology are also explained, along with the role of CTS in EDA tools.

Clock distribution and routing is important in digital design as it impacts Power, Performance and Area (a.k.a PPA) of the SOC design. The Clock Tree Synthesis (CTS) process impacts maximum operating clock frequency through the clock skew. Process Variation generated race-around conditions are avoided through CTS. In test mode, many flip-flops are hooked together to form a scan chain. The skew requirements of scan-chain are stringent for the scan clock tree as every path during test mode is a short  path. The clock tree network is responsible for a significant amount of power dissipation as it switches most frequently. Clock trees are good candidates for low power VLSI designs.

CTS in VLSI Design Flow:

Now lets see exactly where in the VLSI flow CLOCK Tree Synthesis is done. First take a look at the VLSI Design Flow. 

From above flow we can understand that CTS is done in between Placement and Routing. 

Clock Tree Synthesis :

Clock spine routing scheme with all clock pins driven directly from the clock driver. FPGAs often use this fish bone type of clock distribution scheme. A clock spine for a gate array.

A clock spine for a cell-based ASIC. Typical chips have thousands of clock nets. A clock spine is usually driven from one or more clock-driver cells. Delay in the driver cell is a function of the number of stages and the ratio of output to input capacitance for each stage (taper). Clock latency and clock skew. An Engineer tends to minimize both latency

and skew.

Pre & Post CTS : 

There is a clock root and without CTS clock signal goes to each end leaf cells or FlipFlops directly from clock root. After CTS there are number of buffers inserted so that proper power management could be done.  

Various Levels During CTS:

Above diagram shows various levels of the clock network during CTS. Synthesizing required intermediate buffers are the basic objective of CTS process.  

CTS Methodology:

In order to reduce iterations & TAT , clock tree designs methodologies are developed by engineers. This can consist of sub steps : design of the tree structure, layouting the clock tree and synchronization of multiple trees of the same clock source. 

In details the steps can be :

1. Generate Netlist with Specific Number of Receivers in              Clock Tree.

2. Design the tree structure from bottom up process.

3. Use the layout tool features to form the clock tree.

4. Through analysis of delay and skews for all clock nets.

5. Iterate with correction until target is achieved.

CTS In EDA Tool:

EDA toold are used for CTS. Clock Specification File is used. Spec generation option is also available there.

Above diagram shows EDA tool GUI.

Watch the video lecture here:

Courtesy: Image by www.pngegg.com

                  

Read More

What Is Standard Cell Characterization?

 

This article provides a comprehensive guide to Standard Cell Characterization in VLSI design for beginners. The discussion begins with a concise overview of Standard Cell Characterization and highlights how Standard Cells are the building blocks of ASIC (Application-Specific Integrated Circuit) design. Then it moves on to explain the Standard Cell Design Flow and delves deeper into the concept of Handcrafted CMOS Layout. The types of cells present inside the library and variations in cell design, such as VT, Track, and Drive Strength, are also explored. The Front-End View Generation and Back-End View Generation processes are explained, along with the creation of Liberty files. The article also provides an overview of what happens in Characterization and the concept of a cell .lib Library (Liberty). Finally, a summary is provided, outlining the key points covered in the discussion.

Standard Cells : Building Block of ASIC

Standard cells are the building blocks of ASIC designs. We can understand this with a simple analogy shown in above figure of Lego blocks kids loves to play with. A  chip is built with different types of IPS and majority of them are standard cell IPs.

Standard Cell Libraries are required by all tools used in the ASIC Design RTL-to- GDS flow. It contains primitive cells as well as complex cells too. Standard Cells are designed by Variation of Power-Performance-Area (PPA). For each cell a variety of drive strengths are present. Inverters and Buffers have much Larger drive strengths varieties than any outer cells. Cells contains balanced rise and fall delays. Cell with delay variation present to aid fixing of STA violations. Standard Cell heights(dimensions) are denoted by Track. Variation may be 7T , 11T etc. The distance between two consecutive tracks is called the Pitch.

Standard Cell Design Flow:

This is the design flow of standard cell. The flow starts with specification/requirement. It includes all the information which is necessary for the standard cell. After that either schematic or RTL design is done. Schematic is for analog standard cell and RTL design is for digital standard cell. Next we do the CDL or RTL simulation to get the electrical characteristics. The SPICE-OUT step is for schematic or CDL to get the spice netlist. After that HSPICE/Spectre/Eldo simulation is done on spice netlist. 

After frontend, backend flow starts and layout is drawn using Virtuoso. Then we do DRC/LVS , RC Extraction and Physical verification. In Physical Verification we go for antenna checks , EM checks etc. Once all these checks are done we can move to characterization and standard cell delivery.

Handcrafted CMOS Layout :

For PMOS there is N-well and P -select whereas for NMOS there is N-select. Inside N and P select  diffusion layers and Source and Drain contacts are created as shown above. Before creating contacts all the steps involved are in FEOL. After that Poly gates are created and connected with each other see Fig 4b. At final steps  Vdd, GND and Vout connections are created see Fig 4c. Connection between transistors , Source or  Drain contact creation and Poly gate creation and connection all are included in MEOL. Any step  beyond output contact creation is included in BEOL.

Types of Cells Inside The Library:

A standard cell library usually have Basic logic gates such as AND/OR/NAND, Half adder/Full adder, Multiplexer, ECO cells (specially used for ECO or Electronic Change Order), Tie Cells, AOI/AND-OR Inverter, OAI/ OR-AND Inverter, Flip flops, Scan Flops, Latches, Filler Cells, Tap Cells, End Cap Cells, D -Cap Cells, Clock cells.

Cell Design Variation : VT

Threshold voltage is varied in standard cell design. Ultra low Vt, Low Vt, Standard Vt, High Vt and Ultra High Vt are some Vt variations.

Cell Design Variation : Track

Track or height is another parameters that is varied in standard cells. According to ascending order of cell  12.5T> 10.5T> 9T, 7.5T, 6T. More the track number the height of the cell is higher and area of the cell is bigger.  

 

Cell Design Variation : Drive Strength

Drive strength or drivability of a cell is the third parameter to vary. Drivability means how many output a particular standard cell can drive. 

Front-End View Generation : 

Some front end views available in standard cell library are RTL views like Verilog, VHDL,  SystemVerilog, DB, SDB, SLDB,UPF,CPF,OA etc. 

Back-End View Generation : 

Layout views, Mapping File, NDM, GDSII, LEF, DEF, DB OASIS, CIF, Abstract View are some backend views present in standard cell distribution. Physical verification related views and tool related views could be there.

How Liberty File is Created ?

Liberty file is used in timing analysis. standard cell library is passed through the .lib characterization process and finally we get a ASCII file with .lib extension. This file is in liberty format.

What Happens in Characterization?

We have our basic gates and our netlist which are passed on to characterization engine.  There is a TCL config file which contains all setup info and list of runs need to take place. Then the engione is connected to LSF/UGE, these are load sharing facility runs with token assigned to teams. Since these runs requires lot of memories , high memory machines are used and LSF knows which one to select. Its a setup abvailable in companies and system people takes care of it. Engineers just need to understand how to properly use it. From LSF the whole process launches multiple spice simulation and cumulative result comes back.After that we proceed towards model generation. NLDM, CCS, ECSM, OCV are some common model that is generated. All these data are put in the ASCII format in .lib file. 

Cell .lib Library (Liberty):

Timing Engine Reads a set of Cell Library files (.lib).The .lib file is a text file containing timing and power parameters  associated with any standard cell for a given technology node. It contain the data for all standard cells available to the design in the specified technology node. So , each instance in the verilog/vhdl/systemverilog netlist must have a corresponding cell found in the .lib library. The .lib file contains pre-characterized timing models and data to calculate I/O Delay paths , Timing Check Values & Interconnect Delays,To compensate the PVT and OCV variation de-rating factors are also included.

Summary :

Standard Cell Library is a collection of Basic as Well As Advanced Cells. Standard Cells will contain Consolidated Timing Library (.lib) for all the cells . This is the major product of the Characterization. One particular cell will have multiple views and variations based on parameters like Track/VT/Drive Strength. Standard Cells are the biggest IP collection by volume among all Foundation IPs. Hence its characterization is also cumbersome and time consuming. Without the Characterized Standard Cell Library the Digital VLSI SOC Design is impossible !

Watch the video lecture here:

Courtesy: Image by www.pngegg.com

Read More