Power Optimization Methodologies in CMOS ! Power Management 2

The article delves into crucial aspects of power optimization in CMOS circuits. In this atricle, we have explored various strategies for optimizing power in electronic circuits comprehensively. We started with an overview of power optimization circuits, touching on key low power design methodologies and examining the extensive power reduction design space. We delved into the concept of power states, discussing techniques such as voltage scaling, multi-voltage scaling, and power gating, which are crucial for reducing power consumption. Further, we covered clock tree optimization and clock gating, as well as advanced transistor techniques like dual, multi, and variable threshold MOSFETs and transistor stacking. The discussion also included the use of special cells for power optimization, interconnect strategies, and the tools available for implementing these power optimization techniques.

Low Power Design Methodologies : 

Whatever power goes inside the IC comes out as heat. Continues current flow in the circuit increases junction temperature and that heat must be dissipated. That dissipation happens through the packaging. Power optimization in IC is a must otherwise the heat dissipation If the chip Packaging and its costs, Power supply rail design, 

- Chip and system cooling costs

- Noise immunity and system reliability

- Battery life (in portable systems)

In VLSI design circuit speed has been considered as performance metric. Power considerations has become ultimate design criteria in portable applications. Aim of these applications is to maximize battery life time, with minimum power. LPD also need to reduce the power in high-end systems with huge integration density and thus improve the speed of operation. Digital systems design is spread over multiple steps from system to process level. To optimize power (specifically for LPD), the method should be applied over all steps. It is very important to have knowledge about the power distribution. So the blocks or parts consuming fraction of power could be clearly optimized for saving power.

Power Reduction Design Space : 

1. Power reduction through system integration :

- Utilize low system clocks

- Use high level of integration

- Integrating off-chip memories (ROM, RAM, etc.) and other ICs such as digital and analog peripherals.

2. Power reduction by algorithm level :

- Minimizing the number of operation. That reduces the number of H/W resources

- Data coding for reduce the switching activity.

3. Power reduction through architectural model :

- Power management by shutting down unused blocks

- Low-power architectures based on parallelism, pipelining, etc.

- Memory partition with selectively enabled blocks

- Reduction of the number of global busses

- Minimization of instruction set for simple decoding and execution.

4. Power reduction through circuit/logic design :

- Reduce switching activity by optimized algorithm

- Optimize clock and bus loading

- Circuit techniques which minimizes number of devices used in the circuit

- Custom design may improve the power

- Reduces VDD in non-critical paths and proper transistor sizing

- Use of multi-VT circuits

5. Power reduction through process technology :

- One way to reduce the power dissipation is to reduce the power supply voltage. Reduction in Vdd increases delay. To match the device with supply voltage scaling is the option.

- The advantages of scaling for LPD are : improved current drive capabilities,

reduced capacitances through small geometries and junction capacitances

- Improved interconnect technology

- Availability of multiple and variable threshold devices

- This results In good management of active and standby power trade-off

- Higher density of integration.

What are Power States : 

An IP performs certain functional jobs. It is designed for that. Since power is the concern for state-of-art appliances we must optimize power for IP operations. To optimize and save power we must understand the usage of any IP first . We can define different operation modes for an IP and accordingly necessary power would differ. Thus operations modes of an IP are also termed as power states.

Depending on functional role of an IP, Power states are defined and power is saved. Power states are defined and differentiated from each other based on corresponding functional mode. Based on usage power is reduced and saved. In some cases, power states can have sub-states.

Voltage Scaling : 

Supply Voltage Scaling :

Used to reduce dynamic and leakage power. Lowers subthreshold current and gate leakage current. The optimal point for power savings using this technique is the lowest voltage which the circuit retains its logic states and does not compromise performance. To achieve low-power benefits without compromising performance, two ways of lowering supply voltage can be employed: the static supply scaling and the dynamic supply scaling.

Static Supply Scaling: ( Voltage Islands)

Multiple supply voltages are used as per operation requirement. Critical and non-critical paths and/or units re clustered and powered accordingly. Whenever an output from a low Vdd unit has to drive an input of a high Vdd unit, a level conversion is required at the interface.

Dynamic Supply Scaling :

This technique uses single supply voltage. Hence cost is less. When performance demand is low, supply voltage and clock frequency are lowered. Substantial power reduction is possible by that. Circuit need to be operable over a wide voltage range. Operating system to intelligently determine the processor speed. Regulator to generate the minimum voltage for specific speed.

Multi Voltage Scaling :

Dynamic Voltage and Frequency Scaling (DVFS):

A larger number of voltage levels are dynamically switched to follow changing workloads.

Adaptive Voltage Scaling (AVS):

An extension of DVFS where a control loop is used to adjust the voltage.

Multi-Voltage Design Challenges :

1. Level shifters: Signals that go between blocks that use different power rails require level shifters.

2. Characterization and STA: Need libraries for each voltage and level shifter configuration.

3. Floorplanning: Complex power planning and power grids

4. Board level issues: Need additional regulators to provide the additional supplies.

5. Power up and power down sequencing: There may be a required sequence for powering up the design.

Power Gating : 

One of the technique to reduce the leakage power. In this technique a MOSFET switch or sleep transistor is used to cut off/gate, a circuit from the power rails (Vdd and/or gnd) during standby mode. The switch typically is positioned as header between the circuit and the Vdd or as footer between the circuit and the ground. Power gating has the basic strategy of providing Sleep/Stand By mode & Active mode. During active operation, the power gating switch remains on, supplying the current that the circuit uses to operate. During standby mode, turning off the power gating switch reduces the current dissipated through the circuit.

Clock Tree Optimization & Clock Gating :

Clock signal is the most fundamental signal for any digital circuit and Clock signal consumes the most amount of the total power. The design of clock network is important in order to make the low power system achieve good functional stability under low voltage. Clock distribution is crucial for timing and design convergence. Most of the power is consumed due to the high clock frequency used for operating the device. Up to 70% or even more of the dynamic power can be spent in the clock buffers. This is a critical problem in every synchronous circuit. Portions of the clock tree that are not being used at any particular time can be disabled to save the power. This is clock gating and its an effective way of reducing the dynamic power dissipation.

 One of the ways to achieve this is by masking the clock that goes to the idle portion of the circuit. Clock gating is particularly useful for registers that need to maintain the same logic values over many clock cycles. The main challenges of clock gating are finding the best places to use it and creating the logic to shut off and turn on the clock at the proper times.

Dual/Multi/Variable Vth MOSFET : 

The present-day process technology allows the fabrication of MOSFETs of multiple Vt on a single chip. Dual-Vt CMOS circuits is used for high-performance and low-power CMOS circuits. High-Vt transistors used to reduce leakage current and low-Vt transistors to achieve high performance. There are various fabrication technique for implementing multiple Vt MOSFETs in a single chip. 

1. Multiple Channel Doping : Commonly used technique for realizing multiple-VT MOSFETs is to use different channel doping densities

2. Multiple Oxide CMOS : Vth has a dependence on the value of Cox. Different Cox can be realized by using different Tox and accordingly Vth will be different.

3. Multiple Channel Length : Vth decreases as the channel length is reduced, known as Vth roll-off. This phenomenon is exploited to realize transistors of dual threshold voltages.

4. Multiple Body Bias : When the substrate and the source has a voltage difference that leads to an increase or decrease of the threshold voltage.

Multi-Threshold CMOS (MTCMOS) is a popular power gating approach that uses high Vth devices for power switches . Variable threshold CMOS is a body biasing based design technique.

Transistor Stacking : 

Subthreshold leakage current flowing through a stack of series connected transistors reduces when more than one transistor in the stack is turned off. This effect is known as “stacking effect”. Consider a two transistor stack. When both M1 and M2 are turned off, the voltage at the intermediate node (Vx) is positive due to a small drain current. 

Positive potential at the intermediate node has three effects:

1. Due to the positive source potential Vx, gate-to-source voltage of transistor M1 (Vgs1) becomes negative; hence, the subthreshold current reduces substantially.

2. Due to Vx > 0, bulk-to-source potential (Vbs1) of transistor M1 becomes negative, increasing the threshold voltage (Vth) (larger body effect) of M1, and thus reducing the subthreshold leakage. 

3. Due to Vx > 0, the drain-to-source potential (Vds1) of transistor M1 decreases,increasing Vth (less DIBL) of M1, and thus reducing the subthreshold leakage. The leakage of a two-transistor stack less than the leakage in a single transistor.

Special Cells & Power Optimization : 

1. Retention Cell : 

Memories or registers are not capable of keeping their information while powered off. When a particular power domain inside chip is switched off, it is bound to loose its memory. To save such scenarios special retention cells have been adopted in most of the commercial standard cell libraries (eg. TMSC, UMC, GF), to support the State retention power-gating (SRPG). Retention cells store the last state before power off of a flop inside the power domain. Thus it allows the system to continue its operation from the last known state and faster wake up of a block. The only Drawback is the Retention Mode consumes little more current than power off mode.

2. Isolation Cell :

Inter-domain signals can become complicated if the connecting interface changes during different power modes. During Power Gating operation, the circuit will contain few ON and OFF domains together at any point of time. In such situation, output of a OFF domain sends invalid signal to the ON Domain. To deal with such problematic situation Isolation Cell is placed between power gated block and the active block. An Isolation Cell clamps the signal at its input pin to a defined known state, either logic "0 ‟ or logic "1". Hence transmission of invalid signal is eradicated.

3. Level Shifters Cell :

In multi voltage/power domain system, the logic gates on noncritical paths are operated with low VDD and gates on critical path are operated with high VDD. Chip with different supply voltage domains use level shifters to convert and propagate logic signals among different power domains.

4. Always On cells :

An "always on" cell in VLSI is designed to always remain powered on and active, regardless of the state of other cells or the input signals to the chip. These cells are typically used to provide critical functions that must be maintained even when the rest of the chip is in a low- power or sleep mo de, such as maintaining a clock or managing power domains.Such cells are carefully designed to minimize their power consumption while still providing the required functionality. Such Cells are like normal buffers with an extra secondary always-on pin to keep the cells ‘on’ even when primary power is off in a domain. This will remain ‘on’ through the secondary backup supply pin, which supplies the necessary current when the main supply is not available.

Interconnect & Power Optimization : 

Interconnect-power reduction : A circuit consumes switching power Pswitch when the interconnection capacitances are charged and discharged. The interconnect power occupied more than half of the total dynamic power consumption Pdynamic ,with 90% of it contributed from 10% of the interconnections. To reduce Cdyn , larger wire spacing and minimal length routing were implemented for the high-power consuming interconnects.

Net ordering and wire space optimization :To optimize power consumption, interconnect capacitance must be reduced. That can be achieved by rearranging the wire positions I.e net ordering and wire space optimization. Signals with high switching activity (SA) share a relatively larger space than those with lower SA .

Tools & Power Optimization : 

Commercial EDA tools effectively support power management techniques. They also provide additional power savings during implementation. Low power VLSI designs can be achieved at various levels of the design abstraction from algorithmic and system levels down to layout and circuit levels. Varieties of power analysis tools are available to estimate the power of a design.  All commercial tool vendor have such tools. The power products are tools that comprise a complete methodology for low power design. Such tool offers power analysis and optimization from RTL to the gate level. Some tool provides transistor-level power analysis. Activity/switching rate are the basis of analysis for some power tools. In traditional flow each tool has their own low power design commands although there core description might be inconsistent. UPF is used in all tools for obtaining consistent low power consumption design requirements.  Tools can be automatically inserted according to UPF description during FE integration.  MTCMOS is inserted and connected in rear-end realization tools.  Complex power connection, control signal connection are automatically realized according to UPF description. The operation is simple and convenient with high accuracy.

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Power Dissipation in CMOS Technology : Power Management 1

This article delves into crucial aspects of power dissipation in CMOS circuits. In the deep submicron (DSM) and nano-scale era of semiconductor technology, power dissipation has emerged as a critical challenge due to the increasing transistor density and higher operational frequencies. The sources of power dissipation in this context include dynamic components like switching power dissipation, which occurs during the charging and discharging of capacitive loads, and short circuit power dissipation, which happens when both NMOS and PMOS transistors conduct simultaneously during transitions. Additionally, glitching power dissipation arises from unwanted switching events caused by logic hazards. Static power components, contributing to leakage power, encompass various phenomena such as reverse diode leakage current, sub-threshold leakage current, Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Leakage (GIDL), punch through, gate oxide tunneling, and hot-carrier injection. Leakage power is particularly problematic as it leads to increased power consumption, thermal management issues, reduced battery life, reliability concerns, and potential performance degradation, making its management essential for modern electronic devices.

Power Dissipation in DSM/Nano Era : 

Portable computers, wearable electronics gadgets, wireless devices have become much more popular recently. Earlier portable devices didn't need much computing power.  Power requirement of state-of-art portable devices are comparable to their non-portable counterparts. For real time use scenario batteries must last longer. Making batteries that runs longer is an one big challenge. Figuring out how to manage power use is another big challenge. Power dissipation becoming more and more prominent issue. It's harder to deal with the heat and keep things cool because the amount of power being used in a given area is increasing. Integrated circuit is composed by : sequential ckt. , combinational ckt., memory blocks and I/O devices. All have different power consumption rate. 

Power consumption in the logic circuits :

1. 40 % in sequential blocks ,

2. 30 % in combinational parts ,

3. 20% in memory blocks,

4. 10% in I/O devices.

Sources of Power Dissipation : 

Power consumption is determined by : frequency f, supply voltage V, capacitance C, leakage, and short circuit current. Two types of power dissipation : (i) Dynamic & (ii) Static  Power dissipation.

Dynamic power dissipation: When a circuit is in active state or in use , power dissipation due to change in input is called dynamic power dissipation. Dynamic power dissipation is total outcome of switching power, short circuit power and glitching power dissipation.

Static Power Dissipation: Static power is the power dissipated when the gates are idle or there is no output transition. Static power dissipation is caused by leakage currents. Static Power Consumption related to each gate extremely small although summation of all gates become a significant figure.

Dynamic Power Dissipation

Switching Power Dissipation : 

Dynamic switching power dissipation is caused by charging and discharging of O/P capacitors in the circuit

1. I/P changes from high-to-low i.e 1→0

2. O/P changes from low-to-high, i.e. 0→1

3. PMOS/pull up transistor is ON

4. NMOS/pull down transistor will be OFF

5. Capacitor CL charges through pull up transistor.

6. Charging energy is drawn from the power supply.

7. Part of this energy is dissipated in PMOS device and part        is stored on CL.

1. I/P changes from low-to-high i.e. 0 →1

2. O/P changes from high-to-low, i.e. 1→0

3. PMOS/pull up transistor is OFF

4. NMOS/pull down transistor will be ON

5. Capacitor CL discharges through pull down transistor, and         power will be dissipated at pull down transistor.

Short Circuit Power Dissipation : 

Short circuit power dissipation is generated by the short circuit current flowing through both the nMOS and the pMOS transistors during switching. The short circuit current occurs if a logic gate is driven by the input voltage wave forms with the finite rise and fall times. Thus both the nMOS and the pMOS transistors in the circuit conduct simultaneously for a short period of time during the transitions, forming a direct current path between the power supply and ground. This power dissipation takes place even when there is no load or input parasitic capacitor. Short circuit power dissipation depends on mobility of electrons,channel width& length of transistor, supply and threshold voltage, transition time i.e. rise and fall time of input voltage and frequency of operation.

Glitching Power Dissipation :

Glitching power dissipation occurs due to finite delay. This Power dissipated in the intermediate transitions during the evaluation of the logic function of the circuit. In multi-level logic circuits, the propagation delay from one logic block to the next can cause the input signals to the block to change at different times. Thus, a node can exhibit multiple transitions in a single clock cycle before settling to the correct logic level. These intermediate erroneous outputs lead to a power loss in charging and discharging the output load capacitance.  This can reduce by using tree logic structures instead of chain logic structures.

Static Power Dissipation

Static Power Components:

Static power is caused by leakage currents while the gates are idle i.e , when there is no output transitions. Ideally CMOS gates should not be consuming any power in this mode. In reality, however, there is always some leakage current passing  through the transistors, indicating that the CMOS gates do consume a certain amount of power. Static power consumption, associated with each logic gate is extremely small although the total effect becomes significant when tens of millions of gates are utilized in state-of-art ICs. With decreasing feature size , leakage is increasing. Different components of leakage current :

1. Reverse Diode Leakage Current (I1)

2. Sub-threshold Leakage Current (I2)

3. Drain-Induced Barrier-Lowering Effect (I3)

4. Gate Induced Drain Leakage Current (I4)

5. Punch Through (I5)

6. Gate Oxide Tunnelling Current (I6)

7. Hot Carrier Injection (I7)

Reverse Diode Leakage Current:

The reverse diode leakage occurs when the p-n jn. between the drain and the bulk of the transistor is reverse-biased. The reverse-biased drain junction conducts a reverse saturation current which is drawn from the power supply. Reverse leakage current is expressed as:

Vbias is the reverse bias voltage across the jn. , JS is the reverse saturation current density, and A is the junction area. Since the leakage current is proportional to the junction area, it is advisable to minimize the area as much as possible in the layout. The reverse saturation current density is exponentially proportional to the temperature.

Sub-threshold Leakage Current:

Also known as the weak inversion current. Current flows from drain to source. Occurs when the gate voltage is below the threshold voltage VTh. The sub-threshold leakage current can be approximately formulated as:

Where μ0 is the zero bias mobility, Cox is the gate oxide capacitance, and (W/L) represents the width to the length ratio of the leaking MOS device. VT is the thermal voltage constant, and Vgs represents the gate to the source voltage. The parameter η in eqn subthreshold swing co-efficient given by 1 + Cd/Cox with Cd being the depletion layer capacitance of the source/drain junction.  Sub-threshold leakage current is exponentially proportional to (Vgs-VTh). Traditionally, the threshold voltage VTh has been high enough that with Vgs = 0, the sub-threshold current is very small. With state-of-art technology node, reduced power supply voltages require the VTh to be reduced also, and thus, the sub-threshold leakage at Vgs = 0 becomes significant.  Sub-threshold leakage can be reduced by increasing the VTh or reducing the Vgs. However, increasing the VTh affects performance, so there is a strong trade off between performance and the power dissipation of a design.

Drain-Induced Barrier-Lowering Effect (I3):

DIBL occurs when drain depletion region interacts with source near channel surface. Source potential get lowered. Source injects carriers into channel without influence of gate voltage - DIBL enhanced at higher Vd and shorter Leff. Surface DIBL happens before deep bulk punch through. DIBL lowers VT for short channel devices. Higher surface, channel doping and shallow junctions  reduce DIBL leakage current mechanism.

Gate-Induced Drain Leakage (I4):

The GIDL current arises in the high electric field under the gate/drain overlap region which causes a depletion.  GIDL occurs at a low VG and high VD bias and generates carriers into the substrate and drain from the surface traps. Generates carriers into substrate from surface traps, band-to-band tunneling Localized along channel width between gate and drain  Seen as “hook” in I-V characteristic causing increasing current for negative VG - Thinner oxide, higher VDD, lightly-doped drain enhance GIDL

Punch Through (I5) :

Its a break down mechanism. Occurs when the sum of depletion layer width for source and drain junctions is comparable to the channel length. The depletion region of the drain and source junctions gradually merge together as the drain voltage is increased, causing current to flow irrespective of Vg at high Vd. Gate loses control.  Current varies quadratically with drain voltage.

Gate Oxide Tunneling (I6):

High E-field Eox can cause direct tunneling through gateoxide or Fowler-Nordheim (FN) tunneling through oxide bands - Typically, FN tunneling at higher field strength than operating conditions. Significant at Tox < 5 nm - Become dominant leakage mechanism as Tox get thinner - High K dielectrics is alternative.

Hot-Carrier Injection(I7):

Hot carrier is a generic name for high-energy hot electrons and holes generated in the transistor. Hot Carrier is easily generated when the Vg < Vd/2 . When Vd> Vg, the carriers present in the channel will impact the Si crystal lattice and generate pairs of a hot electron and a hot hole (Impact Ionization). These pairs function as hot carriers. Hot carriers under strong Vd gain enough energy to break the barrier of Si/SiO2 inrterface and go through the gate oxide into the gate. As a result, either the gate oxide film is charged, or the Si-SiO2 interface is damaged. This lead to change is transistor characteristic .

Generation mechanism :

1. Channel hot electrons (CHE),

2. Avalanche hot carriers (AHC),

3. Substrate hot electrons (SHE).

AHC shows remarkable change when devices are miniaturized.

Why Leakage Power is an Issue?

Leakage power increases at faster rate than dynamic power (active power) in technology generation and it becoming a large component of total power dissipation. In standby applications leakage power component becomes a significant % of the total power. Earlier leakage power during standby mode is important to reduce but reduction of runtime leakage power is important in deep submicron technology.

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How to Choose Career Path in VLSI?

Choosing a career path in VLSI can be a challenging decision, although there are some steps that can help you make an informed decision:

Research the field: Start by researching the field of VLSI to gain a better understanding of the various roles and job opportunities available. Learn about the industry trends, the types of companies that hire VLSI professionals, and the skills required for different roles.

Understand VLSI Ecosysm First : Click Here

Then Understand ,Various VLSI Job Domains spread accross all these companies : Click Here

Identify your interests and strengths and weakness: Consider your interests, strengths, and skills. Determine what type of work you enjoy doing and what areas of VLSI you are most passionate about. Assess your strengths to determine which roles would be the best fit for you.

Match your skillset/interest with VLSI job roles : Click Here 

Choose between frontend or backend : Click here 

Explore career options: Once you have a better understanding of the VLSI field and your own interests and strengths, explore different career options within the industry. Some of the popular career options in VLSI include Verification Engineer, Design Engineer, Physical Design Engineer, Analog/Mixed-Signal Design Engineer, FPGA Engineer, and System-on-Chip (SoC) Engineer.

Then understand Various Job Roles in VLSI thet you can fit into : Click Here 

Gain experience: To gain a better understanding of the field and the roles available, consider gaining practical experience through internships, co-op programs, or entry-level positions. This will help you build your skills, gain exposure to the industry, and make valuable connections.

Start immediately after 10+2 for VLSI : Click Here 

Search and Apply Internship by yourself by this method : 

Click Here

Build your skills: VLSI requires a range of technical skills, including proficiency in programming languages, hardware design, and simulation tools. Consider taking courses, attending workshops, or pursuing additional certifications to build your skills and stay up-to-date with industry trends. Familiarize yourself with the design tools used in VLSI, such as Cadence, Synopsys, or Mentor Graphics. You can use these tools to create and simulate digital circuits. There are many free or open-source tools available, such as,

1. Vivado (Installation: Click Here), 

2. Electric VLSI Design System, 

3. Icarus-Verilog (Installation : Click Here :), 

4. Magic, NGSPICE (Installation :  Click Here) 

5. OpenTimer (Installtion : Click Here ).

Learn some scripting language,

1. Linux basics for VLSI : Click Here 

2. TCL : Click Here

3. PERL : Click here

4. BASH : Click Here 

Seek guidance: Finally, seek guidance from professionals in the industry or career counselors. They can provide valuable insights into the field and help you make an informed decision about your career path. Additionally, consider networking with professionals in the industry to learn about their experiences and gain insights into the industry.

Join this community for networking : Click Here 

Overall, getting started in VLSI design requires a strong foundation in digital electronics and computer architecture, knowledge of HDLs, familiarity with design tools, practical experience through courses and design projects, and a commitment to continuous learning and practice.

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